1. Final Presentation Performed by: Boris Goychman & Eyal Tsin Instructor: Tsachi Martsiano Annual project, Winter 2012

2. * Joint project with physics faculty, deals with an adaptive mirror * The mirror: * Changes Convexity in order to correct distortions of light originated in the atmosphere * Now used for eye retina distortion corrections

3. * Build a system that interfaces with a PC from one end and controls an adaptive mirror on the other. *Adaptive Mirror – contains 59 capacitors to control the shape of the mirror * Learn an approach for practical engineering. * Get familiar with FPGA, Logic Design and board design basics.

4. PC DE2 - FGPA BOARD DLP - USB GUI DLP CHIP ALTERA CHIP D2A HV S&H Part A Part B

5. Sample & HoldFPGAD2ADLP-USB 4.15us per channel 50Mhz 460ns per channel 1Mbps Data transfer rates Up to 300V3.3V5V3.3V Supply voltage 240mW217mW3mW125uW Power consumption D/A Adaptive Mirror USB D/A Sample & Hold FPGA PC FPGA Interfaces Scope DVM 1. Simulation - ModelSim 2. Emulation for each external component 1. Emulation 2. scope 1. Read from dat file (signal tap) 2. Write to FPGA FIFO Test requirements

7. * Microprocessor * Philips provide software and drivers, easy to implement * Need to buy one + external RAM * Board design * FPGA design * Predesigned board * Difficult to test and design with VHDL * Choosing alternative USB control – ISP * Difficult interface * Higher rate (12Mbps)

8. * VHDL implementation * At least 4 FSM’s and some TBs * FPGA implementation selected * Due to availability * DLP_USB_245 * Simple FIFO – works!

9. * Control a 59 capacitor adaptive mirror * 256 voltage values for each capacitor * Same controller can be used to control any other system with the same requirements * 59 inputs or less * 256 values per input * The output of the D2A will pass through * a SAMPLE & HOLD (not in the scope of part A) * and then to the mirror (not in the scope of part A)

11. DLP’s FIFOFPGA’s FIFO MANAGER FISRT 8bit LAST 8bit FIRST 600 52 D2A HV_A 5 bit control 8 bit control HV_B 5 bit control 8bit 6bit capacitor 8bit voltage 00 6bit capacitor 8bit voltage 00 59 ערכים חבילת עדכון אחת של הקבלים במחשב 8bit 8 bit control 1*1* 600 52 1*1* 8bit USB transfer * בוחר את אחד ה-HVים

12. D[7..0] wrreq rdreq full Q[7…0] empty D_inout[7..0] sclr Ext_START_KEY0 Ext_SD_KEY1 Ext_RESET_KEY2

13. √ Designed FSM’s and coded VHDL for: √ D2A Controller √ DLP Controller √ FIFO √ HV Controller √ Manager √ Simulated and Emulated FSM’s for: √ D2A Controller √ DLP Controller √ DLP Controller + FIFO √ DLP Controller + FIFO + Manager √ HV Controller

14. √ Tested FSM’s with: √ D2A+DVM √ Emulation + Leds + 7 segment √ Signal Tap

15.  Design and test the analog electric circuits :  D2A support circuit  DLP (USB) support circuit  HV support circuit  MUX, RELAY and SWITCH support circuits  300V, +15V and -15V power supply  Integrate and test every-thing