1. DSM Design and Verification Flow
Lecture 21
Alessandra Nardi

2. Outline Conventional design flow review Emerging problems
Emerging design flow
Design methodology challenges
Signal Integrity
Reliability
Manufacturability
Power

3. Conventional Design Flow
Funct. Spec
Logic Synth.
Gate-level Net.
RTL
Layout
Floorplanning
Place & Route
Front-end
Back-end
Behav. Simul.
Gate-Lev. Sim.
Stat. Wire Model
Parasitic Extrac.

4. Verification at different levels of abstraction
Behavioral
HDL
System Simulators
HDL Simulators
RTL
Code Coverage
Gate-level Simulators
Gate-level
Static Timing
Analysis
Physical
Domain
Layout vs
Schematic (LVS)
Verification

5. Verification Techniques
Goal: Ensure the design meets its functional and timing
requirements at each of these levels of abstraction
Simulation (functional and timing)
Behavioral
RTL
Gate-level (pre-layout and post-layout)
Switch-level
Transistor-level
Formal Verification (functional)
Static Timing Analysis (timing)

6. Classification of Simulators
Logic Simulators
Emulator-based
Schematic-based
HDL-based
Event-driven
Cycle-based
Gate
System

7. Conventional Design Flow
Funct. Spec
Logic Synth.
Gate-level Net.
RTL
Layout
Floorplanning
Place & Route
Front-end
Back-end
Behav. Simul.
Gate-Lev. Sim.
Stat. Wire Model
Parasitic Extrac.

8. Emerging challenges Wire load model
Synthesis flow involves the use of statistical wire-load models:
Wire load models available in the library are a statistical average based on several previous designs
Wire length is a function of the fanout: far from accurate given that fanout are largely design specific
Long and painful to achieve timing convergence between pre-layout and post-layout

9. Emerging challenges Wire load model
The problem of timing convergence can be addressed by using wire-load models specific to the design (aka custom wire-load models)
Custom wire-load model can be obtained by parasitic estimation:
Perform initial placement
Generate estimated loads
Use these to generate custom models
Notice that parasitic estimation is not based on actual routing data (as in the case of parasitic extraction)

10. Emerging challenges Floorplan, Place&Route
Need to achieve timing convergence with minimal number of iterations
Routing in general is an extremely computationally expensive task
Delays are increasingly dominated by interconnects
Transition to a timing-driven placement and route approach
Router must adhere to signal integrity, electromigration, power and other such specifications

11. Emerging challenges Parasitic Extraction
As design get larger, and process geometries smaller than 0.35mm, the impact of wire resistance, capacitance and inductance (aka parasitics) becomes significant
Need to model them
Parasitic extraction follows layout
Large run time involved (trade-off for different levels of accuracy)
Large sizes of files generated (Reduced Order Modeling)

12. DSM design flow

13. More emerging issues
Signal Integrity (SI) : Ensure signals travel from source to destination without significant degradation
Crosstalk: noise due to interference with neighboring signals
Reflections from impedence discontinuity
Substrate and supply grid noise

14. More emerging issues Reliability Manufacturability Electromigration
Electrostatic Discharge (ESD)
Manufacturability
Parametric yield
Defect-related yield

15. More emerging issues Power
Power reduction at RTL level and at gate level
Library-level: use of specially designed low-power cells
Design technique
It is critical that power issues be addressed early in the design process (as opposed to late in the design flow)
Power tools:
Power estimation: (Design Power - Synopsys)
Power optimization: take into consideration power just as synthesis uses timing and area (Power Compiler - Synopsys)

16. Overview Emerging Challenges
Conventional design flow  Emerging design flow
Higher level of abstraction
More accurate interconnect model
Interaction between front-end and back-end
Signal Integrity
Reliability
Power
Manufacturability
Paradigm: Issues must be addressed early in the design flow – no more clear logical/physical dichotomy
 New generation of design methodologies/tools needed

17. The Role of Interconnects in DSM Designs

18. Outline Interconnects parameters description
Circuit models for interconnects
Technology scaling and its impact on interconnects

19. Introduction Interconnect: conductive path
Ideally: wire only connects functional elements (devices, gates, blocks, …) and does not affect design performance
This assumption was approximately true for “large” design, it is unacceptable for DSM designs

20. Introduction Real wire has:
Resistance
Capacitance
Inductance
Therefore wiring forms a complex geometry that introduces capacitive, resistive and inductive parasitics. Effects:
Impact on delay, energy consumption, power distribution
Introduction of noise sources, which affects reliability
To evaluate the effect of interconnects on design
performance we have to model them

21. Interconnects - ResistanceL W
Material
Resistivity [-m]
Silver (Ag)
1.6x10-8
Copper (Cu)
1.7x10-8
Gold (Au)
2.2x10-8
Aluminium (Al)
2.7x10-8
Tungsten (W)
5.5x10-8 H

22. Interconnects - Capacitance
Parallel Plate Capacitance L W H
Dielectric
Substrate
tdi
Keep in mind:
C is proportional to the overlap between conductors
C is inversely proportional to their separation

23. Interconnects - Capacitance
Fringing Capacitance
Dielectric
Substrate H
Dielectric
Substrate
Cpp
Cfr

24. Interconnects - Capacitance
Total Capacitance
Dielectric
Substrate + H w
Keep in mind:
C is proportional to the overlap between conductors
C is inversely proportional to their separation

25. Fringing versus Parallel Plate
Taken from
“Digital Integrated Circuits”, 2nd Edition, Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic
Copyright 2002 J. Rabaey et al.

26. Interwire Capacitance
Taken from
“Digital Integrated Circuits”, 2nd Edition, Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic
Copyright 2002 J. Rabaey et al.

27. Interconnects - Inductance
It can be evaluated with the aid of its definition: v=Ldi/dt
It is possible to calculate the inductancefrom its geometry and its enviroment
A simpler approach relies on the fact that the capacitance c and inductance l (per unit length) are related: cl=em (e and m are the permittivity and permeability of the surrounding dielectric)
Caveat: conductor must be surrounded by a uniform dielectric

28. Simplifications
Inductive effects can be ignored if the resistance is substantial (e.g. a long Al wire with small cross-section) or if the rise and fall times of the applied signals are slow
When the wires are short, the cross-section is large or the material has low-resistivity, a capacitance-only model can be used
When the separation between neighboring wires is large or when wires only run together for a short distance, inter-wire capacitance can be ignored, and all the parasitic capacitance can be modeled as capacitance to ground

29. Electrical Wire Model Ideal Wire:
Simplistic
Useful for early phase of the design
OK for small components, e.g. gates
To study the effects of parasitics we need to model them

30. Electrical Wire Model Lumped vs Distributed

31. Electrical Wire Model – Lumped C
If resistive component is small and switching frequencies are in the low to medium range, it makes sense to consider only capacitive component
Wire still represents an equipotential region
Only impact on perfomance is the loading effect
Popular model C

32. Electrical Wire Model – Lumped RC
If wire resistance is significant, a resistive-capacitive model is needed
Lumped RC model is pessimistic and inaccurate for long interconnect wire
Distributed rc-model is complex and no closed form solution exists
Elmore delay formula: lumped RC comes to help R C

33. Electrical Wire Model – Lumped RC Elmore Delays R2 C2 R4 C4 C3 R3 Ci Ri 1 2 3 4 i
Consider an RC-tree:
The network has a single input node
All capacitors between node and ground
The network does not contain any resistive loop

34. Electrical Wire Model – Lumped RC Elmore Delays R2 C2 R4 C4 C3 R3 Ci Ri 1 2 3 4 i
RC-tree property:
Unique resistive path between the source node s and any other node i of the network  path resistance Rii
Example: R44=R1+R3+R4

35. Electrical Wire Model – Lumped RC Elmore Delays R2 C2 R4 C4 C3 R3 Ci Ri 1 2 3 4 i
RC-tree property:
Extended to shared path resistance Rik:
Example: Ri4=R1+R3
Ri2=R1

36. Electrical Wire Model – Lumped RC Elmore Delay
Assuming:
Each node is initially discharged to ground
A step input is applied at time t=0 at node s
The Elmore delay at node i is:
It is an approximation: it is equivalent to first-order time constant of the network
Proven acceptable
Powerful mechanism for a quick estimate

37. Electrical Wire Model – Lumped RC Elmore Delay
Special case: RC-chain (or ladder)
Shared-path resistance path resistance R1 C1 R2 C2 RN CN
Vin VN

38. Electrical Wire Model – Lumped RC Elmore Delay
Time-constant of resistive-capacitive wire R C R C R C
Vin VN
R=r · L/N
C=c·L/N
Delay of wire is quadratic function of its length
Delay of distributed rc-line is half of lumped RC

39. Electrical Wire Model The Distributed RC-line
The diffusion equation
Taken from
“Digital Integrated Circuits”, 2nd Edition, Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic
Copyright 2002 J. Rabaey et al.

40. Interconnects – Why do we care?
Technology scaling: miniaturization of devices (scale L, W, TOX, VTH)
Device Scaling  Faster, smaller devices
L[mm]=0.35, 0.25, 0.18, 0.12, etc  S0.7
Interconnect Scaling  Larger delays!
Local interconnects: Almost constant
Global interconnects:RC delay goes as 1/S or 1/S3
Also, parasitics give rise to a whole set of signal integrity issues
 Design paradigm shift from device-centric to interconnect-centric

41. Interconnects – Why do we care?
ITRS 2001

42. Modern Interconnect Taken from Copyright 2002 J. Rabaey et al.
“Digital Integrated Circuits”, 2nd Edition, Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic
Copyright 2002 J. Rabaey et al.

43. Example: Intel 0.25 micron Process
5 metal layers
Ti/Al - Cu/Ti/TiN
Polysilicon dielectric
Taken from
“Digital Integrated Circuits”, 2nd Edition, Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic
Copyright 2002 J. Rabaey et al.

44. New Interconnect Materials
Aluminium  Copper
Lower resistivity
Higher immunity to Electromigration
SiO2  Low-k dielectrics

45. Overview DSM challenges Interconnects Emerging design flow
Interconnect-centric design paradigm
Signal Integrity
Manufacturability, Reliability
Power Estimation
Interconnects
Description of parasitics
Wire models
Why do we care
New materials