1. Interfacing ‘C542 DSP to Analog Interface Circuit EE113L Week 3 Rick Huang

2. Week 3 EE113D EE Dept UCLA (c) RL 2 Administrative Stuff Assignments Due today Homework 2 Due next week Homework 3 Floppy Disk Graded Homework 1 Solutions posted on class website Agenda Reader pg45-70,79-84 Analog Interface Circuit Anti-aliasing filter cutoff Sampling rate Programming Interrupts Circular addressing Demo Instruments Experiment B

3. Week 3 EE113D EE Dept UCLA (c) RL 3 As a DSP Programmer Satisfy sampling theorem Program the analog chip For each incoming sample, 1. Read into DSP, 2. Process it, 3. Generate an outgoing sample.

4. Week 3 EE113D EE Dept UCLA (c) RL 4 AIC Functional Block Diagram (TLC320AC01C Data Manual)

5. Week 3 EE113D EE Dept UCLA (c) RL 5 Analog Interface Circuit (AIC/AC01) Programming F S and F LP We choose variables A and B. F S = 10MHz / ( 2 A B ) F LP = 10MHz / ( 80 A ) Equations A B AIC registers Register 1 or A Register 2 or B Code REG1 REG2

6. Week 3 EE113D EE Dept UCLA (c) RL 6 Zeroing out last 2 LSBs A = #0FFFCh & A Any value “and” with “1” is the value itself. Any value “and” with “0” is “0”. The last 2 LSBs are control bits for the AIC.

7. Week 3 EE113D EE Dept UCLA (c) RL 7 AIC Initializations ; part of DLY_AC01.ASM … REGISTER.set0bh; on/off bits REG1.set 124h REG2.set 218h REG3.set 300h REG4.set 405h … AC01INIT: ….eval REGISTER & 1h, SELECT.if SELECT = 1h a = #REG1 call REQ2.endif … AC01INIT.ASM Loads REG1 to Register 1 Loads REG2 to Register 2 Loads REG4 to Register 4 DLY_AC01.ASM Uses REGISTER as a bit-mask to selectively load values into AIC registers

8. Week 3 EE113D EE Dept UCLA (c) RL 8 AIC Setting F S and F LP AC01INIT.ASM: Value format given in pg79+ in Reader or pg2- 20+ in AIC manual Reader/manual states 8 LSBs of Register 1 is programmable. For example A = 12h = 18 B = 12h = 18 F S ? F LP ? You do.... REG1.set 112h REG2.set 212h REG3.set 300h REG4.set 405h REG5.set 501h REG6.set 600h REG7.set 700h REG8.set 801h …

9. Week 3 EE113D EE Dept UCLA (c) RL 9 AIC Setting Input & Output Gain AC01INIT.ASM: Value format given in pg79+ in Reader or pg2- 20+ in AIC manual Reader/manual states Last 2 LSBs controls output gain (dB) Next 2 LSBs controls input gain (dB) For example Gain bits = 5h = 0101b  “01” input gain  0dB  “01” output gain  0dB Overall gain? You do.... REG1.set 112h REG2.set 212h REG3.set 300h REG4.set 405h REG5.set 501h REG6.set 600h REG7.set 700h REG8.set 801h …

10. Week 3 EE113D EE Dept UCLA (c) RL 10 Communications between DSP and AIC XINT: A = trcv ; receive sample A = A << 1 ; processing A = #0FFFCh & A ; masking tdxr = A ; transmit sample return_enable ; end ISR AIC DSP 16 tdxr=A A=trcv

11. Week 3 EE113D EE Dept UCLA (c) RL 11 Interrupt Vector Table (vectors.asm)... bxint return_enable ;54; BSP transmit interrupt nop trint return_enable ;58; TDM receive interrupt nop txint goto XINT ;5C; TDM transmit interrupt nop int3 return_enable ;60; external interrupt int3 nop...

12. Week 3 EE113D EE Dept UCLA (c) RL 12 Experiment B: Part 1 A/D – D/A loop Source Code Main program (sample.asm).sect "vectors".copy "vectors.asm".text start:... waitnop goto wait....copy "ac01init.asm“.end Interrupt Vector Table (vectors.asm) A jump table to interrupt service routine txint interrupt is enabled AC01INIT Routine (ac01init.asm) Loads REG1 and REG2 to Register 1 and 2, respectively

13. Week 3 EE113D EE Dept UCLA (c) RL 13 Experiment B: Part 1 A/D – D/A loop Source Code ; part of SAMPLE.ASM.text start: intm = 1 call AC01INIT pmst = #01a0h sp = #0ffah a = #0 imr = #280h intm = 0 waitnop goto wait XINT:… return_enable Calls a routine, AC01INIT Other initializations But when an interrupt comes (1) executes an interrupt service routine and (2) go back to where it left off

14. Week 3 EE113D EE Dept UCLA (c) RL 14 Experiment B: Part 2 Allowing aliasing Aliasing can happen if 2 F LP > F S F S = 10MHz / ( 2 A B ) F LP = 10MHz / ( 80 A )  2 / 80 > 1 / (2B)  B > 20

15. Week 3 EE113D EE Dept UCLA (c) RL 15 Experiment B: Part 3 Signal Delay How to Delay a Signal

16. Week 3 EE113D EE Dept UCLA (c) RL 16 Experiment B: Part 3 Signal Delay Delay using Circular Buffer n=0n=1 n=2n=3n=4n=5 x(n)123456 y(n)

17. Week 3 EE113D EE Dept UCLA (c) RL 17 Experiment B: Part 3 Signal Delay More addressing mode & instruction Circular addressing Pg 5-15 CPU & Periph “%” modifier BK register, BK=#5 ; part of delay.asm start:… AR1 = #buffer BK = #length A = #0 repeat(#length-1) *AR1+% = A … repeat(#9) Pg 2-14 Algebraic Repeats the next instruction 9 times ; part of delay.asm … receive A = trcv *AR1+% = A A = *AR1 tdxr = A return_enable …

18. Week 3 EE113D EE Dept UCLA (c) RL 18 References Course Reader CPU and Peripherals Reference Volume Algebraic Instructions Reference Volume TLC320AC01C chip Reference Volume