2. Cache performance CS 147 Prof. Lee Hai Lin Wu

3. Cache performance  Introduction  Primary components –Cache hits Hit ratio –Cache misses  Average memory access time

4. Why we use cache memory in a computer? The primary reason: to improve system performance by reducing the time needed to access memory.

5. Cache hits  Definition –Every time the CPU accesses memory, it checks the cache. If the requested data is in the cache, the CPU accesses the data in the cache, rather than physical memory; this is a cache hit.

6. A simple example Every time CPU access memory it checks cache first. CPU check accesses data (not in cache) cache Physical memory

7. Cache misses  Definition: –If the data is not in the cache, the CPU accesses the data from main memory(and usually writes the data into the cache as well). This is a cache miss.

8. Hit ratio  Definition: –The hit ratio is the percentage of memory accesses that are served from the cache. Hit Ratio = #of hits / total Strings

9. Average Memory access time  Symbol: T M

10. Formula for T M  T M = hT c + (1 – h) T p *Tc – cache access time *Tp – physical memory access time *h -- hit ratio (Note: Tc and Tp are always given)

11. Relationship between Hit ratios and Average memory access times  Table: So, increase the hit ratio reduce the average memory access time. h 0.00.10.20.30.40.50.60.70.80.91.0 T M (ns) 6055504540353025201510

12. Calculating the H and T M  We will learn how to calculate the H and T M with two different type of cache * associative cache (FIFO) * two-way set-associative cache(LRU)  Besides, there is a direct mapped cache

13. Example of associative cache (FIFO)

14. Example cont. Given: Tc = 10ns Tp = 60ns From the previous table we get: hits = 7 inputs = 18 ** h (hit ratio) = hits/ inputs = 7/18 = 0.389 ** T M = h Tc + (1 – h) Tp = 0.89*10 + (1 - 0.389) 60 = 40.56 ns

15. Two-way associative set- associative cache(LRU)  Hit ratio h = 0.389  TM = 40.56 ns

16. A simple example for LRU  Since the example from book is kind of hard to understand, we can see the following simple example.

17. Simple example of LRU  3 frame  10 inputs: 1, 2, 3, 0, 2, 3, 1, 3, 0, 4

18. Construct a table  Table Data1230231304 1230231304 123023130 12302213 Hit ***

19. Direct mapped cache  The hit ratio h = 0.167  The TM = 50.67 ns

20. The End!!

21. BUT… You have to remember  How to set up the table for FIFO and LRU  How to calculate – Hit Ratio –Average memory access time Gook luck on finals!!