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Graph partition in PCB and VLSI physical synthesis Lin Zhong ELEC424, Fall 2010
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Outline Graph representation Partition 2
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Graphs A graph G = (V, E) – V = set of nodes – E = set of edges = subset of V V Variations: – A connected graph has a path from every node to every other – In an undirected graph: Edge (u,v) = edge (v,u) No self-loops – In a directed graph: Edge (u,v) goes from node u to node v, notated u v – A weighted graph associates weights with either the edges or the nodes E.g., a road map: edges might be weighted w/ distance David Luebke 3
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Representing Graphs Assume V = {1, 2, …, n} An adjacency matrix represents the graph as a n x n matrix A: – A[i, j] = 1 if edge (i, j) E (or weight of edge) = 0 if edge (i, j) E David Luebke 4
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Graphs: adjacency matrix Example: 1 24 3 a d bc A1234 10ad0 200b0 30000 400c0 David Luebke 5
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Graphs: adjacency matrix The adjacency matrix is a dense representation – Usually too much storage for large graphs – But can be very efficient for small graphs Most large interesting graphs are sparse – E.g., planar graphs, in which no edges cross, have |E| = O(|V|) by Euler’s formula – adjacency list 6
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Graphs in embedded system design Algorithm & Software – Node: Computation – Edge: Input/output (data dependencies) – Embedded system synthesis – Parallel computing Hardware – Node: component – Edge: wire/bus – PCB & IC 7
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PCB & IC physical synthesis A. Kahng 8
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Embedded system synthesis Node: Computation task Edge: Data communication/dependency FPGA ASIC ARMCoreDSP 9
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Load balancing in parallel computing Node: Process Edge: Inter-process communication Core 1 Core 2 Core 3Core 4 Process 1 Process 2 Process 3 Process 4 Process 5 Process 6 10
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Operational research Node: Personnel Edge: Collaboration Building 1Building 2 Building 3Building 4 11
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Partition Constraints – # of partitions – The capability of each partition Objective – Edge cut Wire/interconnection cost – Delay in computation (Software) Too many computations assigned to a core Bipartitioning: 2-way partitioning. Bisectioning: Bipartitioning such that the two partitions have the same size. NP-Complete Problem 12
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Kernighan-Lin (KL) Algorithm Bisectioning Input: A graph with – Set nodes V (|V| = 2n) – Set of edges E (|E| = m) – Cost c AB for each edge {A, B} in E Output: Two partitions X & Y s.t. – Total cost of edges cut is minimized. – Each partition has n nodes NP-Complete D. Pan Kernighan, B. W.; Lin, Shen (1970). "An efficient heuristic procedure for partitioning graphs". Bell Systems Technical Journal 49: 291-307. 13
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Complexity of graph bisectioning Brute-force method: n out of 2n nodes – (2n)!/(n!) 2 = [2n*(2n-1)*…*(n+1)]/n! – =Σ r=0,…,n-1 [(2n-r)/(n-r)] (n+1)≥(2n-r)/(n-r)≥2 The complexity is therefore between O(2 n ) and O(n n ) 14
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Idea of KL Algorithm D A = Decrease in cut value if moving A – External cost (connection) E A – Internal cost I A – Moving A from partition X to Y would increase the value of the cut set by E A and decrease it by I A A B C D XY A B C D XY D A = 2-1 = 1 D B = 1-1 = 0 D. Pan 15
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Idea of KL Algorithm Note that we want to balance two partitions If switch A & B, gain(A,B) = D A +D B -2c AB – c AB : edge cost for AB A B C D XY A B C D XY gain(A,B) = 1+0-2 = -1 D. Pan 16
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Idea of KL Algorithm Start with any initial legal partitions X and Y. A PASS (exchanging each node exactly once) is described below: 1. For i := 1 to n do From the unlocked (unexchanged) nodes, choose a pair (A,B) s.t. gain(A,B) is largest Exchange A and B. Lock A and B for this pass Let g i = gain(A,B). 2. Find the k s.t. G=g 1 +...+g k is maximized 3. Switch the first k pairs. Repeat the PASS until no improvement (G=0). D. Pan 17
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Time complexity of KL For each pass, – O(n 2 ) time to find the best pair to exchange. – n pairs exchanged. – Total time is O(n 3 ) per pass. Better implementation can get O(n 2 log n) time per pass. Number of passes is usually small. D. Pan 18
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Fiduccia-Mattheyses (FM) Algorithm Modification of KL Algorithm: – Allow non-uniform vertex weights (areas) – Allow unbalanced partitions – Extended to handle hypergraphs – Clever way to select nodes to move, run much faster. Input: A hypergraph with – Set nodes V (|V| = n) – Set of hyperedges E – Area a u for each node u in V – Cost c e for each hyperedge in e – An area ratio r (Unbalanced partition) Output: 2 partitions X & Y such that – Total cost of hyperedges cut is minimized – area(X) / (area(X) + area(Y)) is about r C. M. Fiduccia and R. M. Mattheyses. "A linear-time heuristic for improving network partitions". Proc. DAC, pp 174-181, 1982. NP-Complete D. Pan 19
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Hypergraph vs. graph Nodes: A, B, C, D Hyperedges: {A,B,C}, {B,D}, {C,D} Vertex label: Gate size/area Hyperedge weight: importance/cost of net A B CD A B C D D. Pan 20
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Ideas of FM Algorithm Similar to KL – Work in passes. – Lock nodes after moved. – Actually, only move those nodes up to the maximum partial sum of gain Difference from KL – Not exchanging pairs of nodes Move only one node at each time – The use of bucket data structure for gains D. Pan 21
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Time Complexity of FM For each pass, – Constant time to find the best node to move. – After each move, time to update gains is proportional to degree of node moved. – Total time is O(p), where p is total number of pins Number of passes is usually small. D. Pan 22
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Find the optimal bisection 1 X 2 3 4 5 6 Y Original Cut Value = 9 KL Algorithm D. Pan 23
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4 X 2 3 1 5 6 Y Optimal Cut Value = 5 D. Pan 24
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Homework C. M. Fiduccia and R. M. Mattheyses, "A linear-time heuristic for improving network partitions,” Proceedings of the Design Automation Conference, pp 174- 181, 1982 C. M. Fiduccia and R. M. Mattheyses, "A linear-time heuristic for improving network partitions,” Proceedings of the Design Automation Conference, pp 174- 181, 1982 B. Krishnamurthy, “An Improved Min-Cut Algonthm for Partitioning VLSI Networks,” IEEE Transactions on Computers, 1984 B. Krishnamurthy,“An Improved Min-Cut Algonthm for Partitioning VLSI Networks,” IEEE Transactions on Computers, 1984 25
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