1. 1 IKI10230 Pengantar Organisasi Komputer Bab 4.1: Input/Output & Interrupt 19 Maret 2003 Bobby Nazief (nazief@cs.ui.ac.id) Qonita Shahab (niet@cs.ui.ac.id) bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/ Sumber: 1. Hamacher. Computer Organization, ed-5. 2. Materi kuliah CS152/1997, UCB.

2. 2 Input/Output: Gerbang Ke Dunia Luar Processor (active) Computer Control (“brain”) Datapath (“brawn”) Memory (passive) (where programs, data live when running) Devices Input Output Keyboard, Mouse Display, Printer Disk (where programs, data live when not running)

3. 3 Motivation for Input/Output °I/O is how humans interact with computers °I/O lets computers do amazing things: Read pressure of synthetic hand and control synthetic arm and hand of fireman Control propellers, fins, communicate in BOB (Breathable Observable Bubble) Read bar codes of items in refrigerator °Computer without I/O like a car without wheels; great technology, but won’t get you anywhere

4. 4 I/O Device Examples and Speed °I/O Speed: bytes transferred per second (from mouse to display: million-to-1) °DeviceBehaviorPartner Data Rate (Kbytes/sec) KeyboardInputHuman0.01 MouseInputHuman0.02 Line PrinterOutputHuman1.00 Floppy diskStorageMachine50.00 Laser PrinterOutputHuman100.00 Magnetic DiskStorageMachine10,000.00 Network-LANI or OMachine 10,000.00 Graphics DisplayOutputHuman30,000.00

5. 5 What do we need to make I/O work? °A way to connect many types of devices to the Proc-Mem °A way to control these devices, respond to them, and transfer data °A way to present them to user programs so they are useful Proc Mem PCI Bus SCSI Bus cmd reg. data reg. Operating System Windows Files

6. 6 Organisasi I/O ° ° ° ProsesorMemori Control Lines Address Lines Data Lines Address Decoder Control Circuits Data & Status Registers Input Device I/O Interface BUS

7. 7 A Bus is: °shared communication link °single set of wires used to connect multiple subsystems Control Datapath Memory Processor Input Output

8. 8 Review: Organisasi Input/Output Prosesor Bus SOUT DATAOUT Display SIN DATAIN Keyboard °I/O Device biasanya memiliki 2 register: 1 register menyatakan kesiapan untuk menerima/mengirim data (I/O ready), sering disebut Status/Control Register  SIN, SOUT 1 register berisi data, sering disebut Data Register  DATAIN, DATAOUT °Prosesor membaca isi Status Register terus-menerus, menunggu I/O device men-set Bit Ready di Status Register (0  1) °Prosesor kemudian menulis atau membaca data ke/dari Data Register tulis/baca ini akan me-reset Bit Ready (1  0) di Status Register

9. 9 Review: Contoh Program Input/Output °Input: Read from keyboard Move#LOC,R0; Initialize memory READ:TestBit#3,INSTATUS; Keyboard (IN) ready? Branch=0READ; Wait for key-in MoveDATAIN,(R0); Read character °Output: Write to display ECHO:TestBit#3,OUTSTATUS; Display (OUT) ready? Branch=0ECHO; Wait for it Move(R0),DATAOUT; Write character Compare#CR,(R0)+; Is it CR? ; Meanwhile, stores it Branch≠0READ; No, get more CallProcess; Do something

10. 10 Memory-mapped-I/O vs. I/O-mapped-I/O °Status & Data Registers are treated as memory locations: Called “Memory Mapped Input/Output” A portion of the address space dedicated to communication paths to Input or Output devices (no memory there) The registers are accessed by Load/Store instructions, just like memory °Some machines have special input and output instructions that read-from and write-to Device Address Space: Called “I/O Mapped Input/Output” IN R x,Device-Address; Processor  Device ; R x  R device-Address OUT Device-Address,R x ; Device  Processor ; R device-Address  R x

11. 11 Contoh Program Input/Output (I/O-mapped-I/O) °Input: Read from keyboard Move#LOC,R0; Initialize memory READ:InINSTATUS,R1; Read status TestBit#3,R1; Keyboard (IN) ready? Branch=0READ; Wait for key-in InDATAIN,R1; Read character MoveR1,(R0); Store in memory °Output: Write to display ECHO:InOUTSTATUS,R1; Read status TestBit#3,R1; Display (OUT) ready? Branch=0ECHO; Wait for it Move(R0),R1; Get the character OutR1,DATAOUT; Write it Compare#CR,(R0)+; Is it CR? ; Meanwhile, stores it Branch≠0READ; No, get more CallProcess; Do something

12. 12 Polling

13. 13 Processor-I/O Speed Mismatch °500 MHz microprocessor can execute 500 million load or store instructions per second, or 2,000,000 KB/s data rate I/O devices from 0.01 KB/s to 30,000 KB/s °Input: device may not be ready to send data as fast as the processor loads it Also, might be waiting for human to act °Output: device may not be ready to accept data as fast as processor stores it °What to do?

14. 14 Program-Controlled I/O: Polling °Input: Read from keyboard MoveR1,#line; Initialize memory WAITK:TestBitSTATUS,#0; Keyboard (IN) ready? Branch=0WAITK; Wait for key-in MoveR0,DATAIN; Read character °Output: Write to display WAITD:TestBitSTATUS,#1; Display (OUT) ready? Branch=0WAITD; Wait for it MoveDATAOUT,R0; Write character Move(R1)+,R0; Store & advance CompareR0,#$0D; Is it CR? Branch≠0WAITK; No, get more CallProcess; Do something °Processor waiting for I/O called “Polling” OUTIN STATUS DATAIN DATAOUT

15. 15 Cost of Polling? °Assume for a processor with a 500-MHz clock it takes 400 clock cycles for a polling operation (call polling routine, accessing the device, and returning). Determine % of processor time for polling Mouse: polled 30 times/sec so as not to miss user movement Floppy disk: transfers data in 2-byte units and has a data rate of 50 KB/second. No data transfer can be missed. Hard disk: transfers data in 16-byte chunks and can transfer at 8 MB/second. Again, no transfer can be missed.

16. 16 % Processor time to poll mouse, floppy °Times Mouse Polling/sec = 30 polls/sec °Mouse Polling Clocks/sec = 30 * 400 = 12000 clocks/sec °% Processor for polling: 12*10 3 /500*10 6 = 0.002%  Polling mouse little impact on processor °Times Polling Floppy/sec = 50 KB/s /2B = 25K polls/sec °Floppy Polling Clocks/sec = 25K * 400 = 10,000,000 clocks/sec °% Processor for polling: 10*10 6 /500*10 6 = 2%  OK if not too many I/O devices

17. 17 % Processor time to hard disk °Times Polling Disk/sec = 8 MB/s /16B = 500K polls/sec °Disk Polling Clocks/sec = 500K * 400 = 200,000,000 clocks/sec °% Processor for polling: 200*10 6 /500*10 6 = 40%  Unacceptable

18. 18 Interrupt

19. 19 What is the alternative to polling? °Wasteful to have processor spend most of its time “spin-waiting” for I/O to be ready °Wish we could have an unplanned procedure call that would be invoked only when I/O device is ready °Solution: use interrupt mechanism to help I/O. Interrupt program when I/O ready, return when done with data transfer

20. 20 I/O Interrupt °An I/O interrupt is like a subroutine call except: An I/O interrupt is “asynchronous” More information needs to be conveyed °An I/O interrupt is asynchronous with respect to instruction execution: I/O interrupt is not associated with any instruction, but it can happen in the middle of any given instruction I/O interrupt does not prevent any instruction from completion

21. 21 Interrupt Driven Data Transfer (1) I/O interrupt (2) save PC (3) interrupt service addr Memory add sub and or user program read store... jr interrupt service routine (4) (5)

22. 22 Interrupt Service Routine (Interrupt Handler) Main Program Move#Line,PNTR; Initialize buffer pointer. ClearEOL; Clear end-of-line indicator. BitSet#2,CONTROL; Enable keyboard interrupts. BitSet#9,PS; Set interrupt-enable bit in the PS. … Interrupt Service Routine Read: MoveMultipleRO-R1,-(SP); Save R0 & R1 on stack. MovePNTR,R0; Load buffer pointer. MoveByteDATAIN,R1; Get input character and MoveByteR1,(R0)+; store it in the buffer. MoveR0,PNTR; Update buffer pointer. CompareByte#$0D,R1; Check if Carriage Return Branch≠0RTRN Move#1,EOL; Indicate end-of-line. BitClear#2,CONTROL; Disable keyboard interrupts. RTRN: MoveMultiple(SP)+,RO-R1; Restore R0 & R1. Return-from-interrupt

23. 23 Benefit of Interrupt-Driven I/O °400 clock cycle overhead for each transfer, including interrupt. Find the % of processor consumed if the hard disk is only active 5% of the time. °Interrupt rate = polling rate Disk Interrupts/sec = 8 MB/s /16B = 500K interrupts/sec Disk Transfer Clocks/sec = 500K * 400 = 200,000,000 clocks/sec % Processor for during transfer: 250*10 6 /500*10 6 = 40% °Disk active 5%  5% * 40%  2% busy  Determined by disk’s activity, whereas in Polling- driven I/O the Processor will be busy polling 40% of the time even if the disk is not active

24. 24 Instruction Set Support for I/O Interrupt °Save the PC for return To enable the “proper return” when the interrupt has been served AVR uses the stacks °Where to go when interrupt occurs? To allow “proper branch” to the service routine AVR defines: -Locations 0x000 – 0x002 for external interrupts -Locations 0x003 – 0x00C for internal interrupts °Determine cause of interrupt? To guarantee “proper service routine” serving “proper interrupt” AVR uses vectored interrupt, which associates the location of the interrupt service routine (see above) with the device that causes it

25. 25 Interrupt Hardware

26. 26 Interrupt Request Processor INTR1 °I/O Devices interrupt processor through a single line known as Interrupt Request signal (INTR) °To serve n devices, the line uses wired-or connection that allows any interrupting device to activate the signal any INTR i is switched on, INTR will become TRUE INTRn INTR2 V dd INTR

27. 27 Sequence of Events during Interrupt 1.The device activates interrupt request signal. 2.The processor interrupts the program currently being executed. 3.Interrupts are disabled by changing the control bits in the PS. 4.The device is informed that its request has been recognized, and in response, it deactivates the interrupt request signal. 5.The action requested by the interrupt is performed by the interrupt service routine. 6.Interrupts are enabled and execution of the interrupted program is resumed.

28. 28 Multiple Devices/Interrupts °How to handle simultaneous interrupt requests? Need to have priority scheme °Which I/O device caused exception? Need to convey the identity of the device generating the interrupt °Can processor avoid interrupts during the interrupt routine? In general, interrupts are disabled whenever one is being serviced; interrupts will be enabled after the service is completed However, occasionally a more important interrupt may occur while this interrupt being served °Who keeps track of status of all the devices, handle errors, know where to put/supply the I/O data? In general, these is one of the tasks of Operating System

29. 29 Device Identification CPU Device 1 Device N Device 2 INTR1 °The Interrupting Device may provide its identity through: Interrupt-Request (IRQ) bit in its Status Register, which will be evaluated one-by-one by the processor (polling) Sending special code the the processor over the bus (vectored interrupt) INTRn INTR2 wired-OR

30. 30 Prioritized Interrupt: Daisy Chain Scheme °Advantage: simple °Disadvantages: Cannot assure fairness: A low-priority device may be locked out indefinitely CPU Device 1 Highest Priority Device N Lowest Priority Device 2 INTA Release INTR wired-OR

31. 31 Prioritized Interrupt: Priority Groups CPU Device 1 Device N Device 2 INTA1 INTR1 °Interrupt Nesting: an Interrupt Service Routine may be interrupted by other, higher-priority interrupt INTA2 INTR2

32. 32 Exceptions

33. 33 Exceptions °Interrupt is only a subset of Exception Exception: signal marking that something “out of the ordinary” has happened and needs to be handled °Interrupt: asynchronous exception Unrelated with instruction being executed °Trap: synchronous exception Related with instruction being executed To recover from errors: Illegal Instruction, Divide By Zero, … To debug a program To provide privilege (for Operating System)

34. 34 I/O & Operating System °The I/O system is shared by multiple programs using the processor OS guarantees that user’s program accesses only the portions of I/O device to which user has rights (e.g., file access) °Low-level control of I/O device is complex because requires managing a set of concurrent events and because requirements for correct device control are often very detailed OS provides abstractions for accessing devices by supplying routines that handle low-level device operations °I/O systems often use interrupts to communicate information about I/O operations OS handles the exceptions generated by I/O devices (and arithmetic exceptions generated by a program) °Would like I/O services for all user programs under safe control OS tries to provide equitable access to the shared I/O resources, as well as schedule accesses in order to enhance system performance

35. 35 I/O – OS – User’s Program I/O Device User’s Program I/O Services Device Driver OS getchar(); System.in.readLine(); putchar(); System.out.println(); Device Driver

36. 36 OS Interrupt Services OSINITSet interrupt vectors Time-slice clock  SCHEDULER Trap  OSSERVICES VDT interrupts  IODATA OSSERVICESExamine stack to determine requested operation Call appropriate routine SCHEDULERSave current context Select a runnable process Restore saved context of new process Push new values for PS and PC on stack Return from interrupt SCHEDULER OSSERVICES IODATA … … PC

37. 37 I/O ROUTINES & DEVICE DRIVER IOINITSet process status to Blocked Initialize memory buffer address pointer Call device driver to initialize device & enable interrupts in the device interface (VDTINIT) Return from subroutine IODATAPoll devices to determine source of interrupt Call appropriate device driver (VDTDATA) If END = 1, then set process status to Runnable Return from interrupt VDTINITInitialize device interface Enable interrupts Return from subroutine VDTDATACheck device status If ready, then transfer character If character = CR, then set END = 1; else set END = 0 Return from subroutine

38. 38 Contoh: Main Program.cseg.org INT0addr rjmpext_int0;External interrupt handler.org OVF0addr rjmptim0_ovf;Timer0 overflow handler main: Do some initializations rcalluart_init;Init UART sei;Enable interrupts idle: sbrsu_status,RDR;Wait for Character rjmpidle Do the work wait: sbrcu_status,TD;Wait until data is sent rjmpwait Wrap it up

39. 39 Contoh: Interrupt Handler ext_int0: ldiu_status,1<<BUSY;Set busy-flag (clear all others) Do some work ldiu_tmp,1<<TOIE0;Set bit 1 in u_tmp outTIFR,u_tmp; to clear T/C0 overflow flag outTIMSK,u_tmp; and enable T/C0 overflow interrupt Do more work clru_bit_cnt;Clear bit counter outGIMSK,u_bit_cnt;Disable external interrupt reti tim0_ovf: sbrsu_status,TD;if transmit-bit set Do something ldiu_tmp,1<<INT0;(u_bit_cnt==9): outGIMSK,u_tmp;Enable external interrupt clru_tmp outTIMSK,u_tmp;Disable timer interrupt cbru_status,(1<<BUSY)|(1<<TD) ;Clear busy-flag and transmit-flag reti