1. Computer Science 210 s1c Computer Systems 1 2014 Semester 1 Lecture Notes James Goodman (revised by Robert Sheehan) Credits: Slides prepared by Gregory T. Byrd, North Carolina State University Input & Output Lecture 13 1

2. 2 Synchronisation  What happens if you try to print a file on a printer already in use?  What happens if your programme tries to read a character before it’s typed?  What happens to a sequence of characters you’ve type in before you read them?  What happens if you send characters to a printer faster than it can accept them?

3. 3 I/O Devices are Cantankerous  Many I/O devices have a mechanical component  They are very slow relative to electronic speeds  They respond when they’re ready, not necessarily when it’s convenient  They may not be willing to wait forever for their input (overrun)  The CPU is the slave: it must synchronize

4. Chapter 8 I/O

5. 5 I/O: Connecting to the Outside World So far, we’ve learned how to:  compute with values in registers  load data from memory to registers  store data from registers to memory But where does data in memory come from? And how does data get out of the system so that humans can use it?

6. 8-6 I/O: Connecting to the Outside World Types of I/O devices characterized by:  behavior: input, output, storage input: keyboard, motion detector, network interface output: monitor, printer, network interface storage: disk, CD-ROM  data rate: how fast can data be transferred? Latency: how long to get the first byte Bandwidth: rate that data is received

7. I/O Device Examples 7 DeviceBehaviorPartnerData Rate (KB/sec) KeyboardInputHuman0.01 MouseInputHuman0.02 Laser PrinterOutputHuman1,000 Graphics DisplayOutputHuman30,000 Network-LANInput or OutputMachine200-100,000 InternetInput or OutputMachine4,o00- ? CD-ROM (1x)StorageMachine150 DVD-ROM (1x)StorageMachine1,352 Magnetic DiskStorageMachine100,000 Flash MemoryStorage-readMachine100,000-300,000 Storage-writeMachine50,000-100,000

8. 8-8 I/O Controller Control/Status Registers  CPU tells device what to do -- write to control register  CPU checks whether task is done -- read status register Data Registers  CPU transfers data to/from device Device electronics  performs actual operation pixels to screen, bits to/from disk, characters from keyboard Graphics Controller Control/Status Output Data Electronics CPU display

9. 8-9 Programming Interface How are device registers identified?  Memory-mapped vs. special instructions How is timing of transfer managed?  Asynchronous vs. synchronous Who controls transfer?  CPU (polling) vs. device (interrupts)

10. 8-10 Memory-Mapped vs. I/O Instructions Instructions  designate opcode(s) for I/O  register and operation encoded in instruction Memory-mapped  assign a memory address to each device register  use data movement instructions (LD/ST) for control and data transfer

11. 8-11 Transfer Timing I/O events generally happen much slower than CPU cycles. Synchronous  data supplied at a fixed, predictable rate  CPU reads/writes every X cycles Asynchronous  data rate less predictable  CPU must synchronize with device, so that it doesn’t miss data or write too quickly

12. 8-12 Transfer Control Who determines when the next data transfer occurs? Polling  CPU keeps checking status register until new data arrives OR device ready for next data  “Are we there yet? Are we there yet? Are we there yet?” Interrupts  Device sends a special signal to CPU when new data arrives OR device ready for next data  CPU can be performing other tasks instead of polling device.  “Wake me when we get there.”

13. 8-13 LC-3 Memory-mapped I/O (Table A.3) Asynchronous devices  synchronized through status registers Polling and Interrupts  the details of interrupts will be discussed in Chapter 10

14. 8-14 Input from Keyboard When a character is typed:  its ASCII code is placed in bits [7:0] of KBDR (bits [15:8] are always zero)  the “ready bit” (KBSR[15]) is set to one  keyboard is disabled -- any typed characters will be ignored When KBDR is read:  KBSR[15] is set to zero  keyboard is enabled KBSR KBDR 15870 140 keyboard data ready bit

15. 8-15 Basic Input Routine new char? read character YES NO Polling POLL LDI R0, KBSRPtr BRzp POLL LDI R0, KBDRPtr... KBSRPtr.FILL xFE00 KBDRPtr.FILL xFE02

16. 8-16 Simple Implementation: Memory-Mapped Input Address Control Logic determines whether MDR is loaded from Memory or from KBSR/KBDR.

17. 8-17 Output to Monitor When Monitor is ready to display another character:  the “ready bit” (DSR[15]) is set to one When data is written to Display Data Register:  DSR[15] is set to zero  character in DDR[7:0] is displayed  any other character data written to DDR is ignored (while DSR[15] is zero) DSR DDR 15870 140 output data ready bit

18. 8-18 Basic Output Routine screen ready? write character YES NO Polling POLLLDI R1, DSRPtr BRzp POLL STI R0, DDRPtr... DSRPtr.FILL xFE04 DDRPtr.FILL xFE06

19. 8-19 Simple Implementation: Memory-Mapped Output Sets LD.DDR or selects DSR as input.

20. 8-20 Keyboard Echo Routine Usually, input character is also printed to screen.  User gets feedback on character typed and knows its ok to type the next character. new char? read character YES NO screen ready? write character YES NO POLL1LDI R0, KBSRPtr BRzp POLL1 LDI R0, KBDRPtr POLL2LDI R1, DSRPtr BRzp POLL2 STI R0, DDRPtr... KBSRPtr.FILL xFE00 KBDRPtr.FILL xFE02 DSRPtr.FILL xFE04 DDRPtr.FILL xFE06

21. 8-21 Interrupt-Driven I/O External device can: (1)Force currently executing program to stop; (2)Have the processor satisfy the device’s needs; and (3)Resume the stopped program as if nothing happened. Why?  Polling consumes a lot of cycles, especially for rare events – these cycles can be used for more computation.  Example: Process previous input while collecting current input. (See Example 8.1 in text.)

22. 8-22 Interrupt-Driven I/O To implement an interrupt mechanism, we need:  A way for the I/O device to signal the CPU that an interesting event has occurred.  A way for the CPU to test whether the interrupt signal is set and whether its priority is higher than the current program. Generating Signal  Software sets “interrupt enable” bit in device register.  When ready bit is set and IE bit is set, interrupt is signaled. KBSR 1514 0 ready bit 13 interrupt enable bit interrupt signal to processor

23. 8-23 Priority Every instruction executes at a stated level of urgency. LC-3: 8 priority levels (PL0-PL7)  Example: Payroll program runs at PL0. Nuclear power correction program runs at PL6.  It’s OK for PL6 device to interrupt PL0 program, but not the other way around. Priority encoder selects highest-priority device, compares to current processor priority level, and generates interrupt signal if appropriate.

24. 8-24 Testing for Interrupt Signal CPU looks at signal between STORE and FETCH phases. If not set, continues with next instruction. If set, transfers control to interrupt service routine (ISR). EA OP EX S S F F D D interrupt signal? Transfer to ISR Transfer to ISR NO YES More details in Chapter 10.

25. 8-25 Full Implementation of LC-3 Memory-Mapped I/O Because of interrupt enable bits, status registers (KBSR/DSR) must be written, as well as read.

26. 8-26 Review Questions What is the danger of not testing the DSR before writing data to the screen? What is the danger of not testing the KBSR before reading data from the keyboard? What if the Monitor were a synchronous device, e.g., we know that it will be ready 1 microsecond after character is written.  Can we avoid polling? How?  What are advantages and disadvantages?

27. 8-27 Review Questions Do you think polling is a good approach for other devices, such as a disk or a network interface? What is the advantage of using LDI/STI for accessing device registers?

28. Computer Science 210 s1c Computer Systems 1 2014 Semester 1 Lecture Notes James Goodman (revised by Robert Sheehan) Credits: Slides prepared by Gregory T. Byrd, North Carolina State University TRAP routines Lecture 14 28

29. Chapter 9 TRAP Routines and Subroutines

30. 9-30 System Calls Certain operations require specialized knowledge and protection:  specific knowledge of I/O device registers and the sequence of operations needed to use them  I/O resources shared among multiple users/programs; a mistake could affect lots of other users!  In real systems we layer our programs using abstraction to make our tasks realistic (APIs).  We want our programs to work with each other (multiple programs running simultaneously). Not every programmer knows (or wants to know) this level of detail Provide service routines or system calls (part of operating system) to safely and conveniently perform low-level, privileged operations

31. 9-31 System Call 1. User program invokes system call. 2. Operating system code performs operation. 3. Returns control to user program. In LC-3, this is done through the TRAP mechanism.

32. 9-32 LC-3 TRAP Mechanism 1. A set of service routines.  part of operating system -- routines start at arbitrary addresses (convention is that system code is “below” x3000)  up to 256 routines 2. Table of starting addresses.  stored at x0000 through x00FF in memory  called System Control Block in some architectures 3. TRAP instruction.  used by program to transfer control to the operating system  8-bit trap vector names one of the 256 service routines 4. A linkage back to the user program.  want execution to resume immediately after the TRAP instruction

33. 9-33 TRAP Instruction Trap vector  identifies which system call to invoke  8-bit index into table of service routine addresses in LC-3, this table is stored in memory at 0x0000 – 0x00FF 8-bit trap vector is zero-extended into 16-bit memory address Where to go  lookup starting address from table; place in PC How to get back  save address of next instruction (current PC) in R7

34. 9-34 TRAP NOTE: PC has already been incremented during instruction fetch stage.

35. 9-35 RET (JMP R7) How do we transfer control back to instruction following the TRAP? We saved old PC in R7.  JMP R7 gets us back to the user program at the right spot.  LC-3 assembly language lets us use RET (return) in place of “JMP R7”. Must make sure that service routine does not change R7, or we won’t know where to return.

36. 9-36 TRAP Mechanism Operation 1.Lookup starting address. 2.Transfer to service routine. 3.Return (JMP R7).

37. 9-37 Example: Using the TRAP Instruction.ORIGx3000 LDR2, TERM; Load negative ASCII ‘7’ LDR3, ASCII; Load ASCII difference AGAINTRAPx23; input character ADDR1, R2, R0; Test for terminate BRzEXIT; Exit if done ADDR0, R0, R3; Change to lowercase TRAPx21; Output to monitor... BRnzpAGAIN TERM.FILLxFFc9; Additive inverse of ASCII ‘7’ ASCII.FILLx0020; lowercase bit EXITTRAPx25; halt.END

38. 9-38 Example: Output Service Routine.ORIGx0430; syscall address STR7, SaveR7; save R7 & R1 STR1, SaveR1 … ; ----- Write character TryWriteLDIR1, CRTSR; get status BRzpTryWrite; look for bit 15 on WriteItSTIR0, CRTDR; write char … ; ----- Return from TRAP ReturnLDR1, SaveR1; restore R1 & R7 LDR7, SaveR7 RET; back to user CRTSR.FILLxFE04; DSR CRTDR.FILLxFE06; DDR SaveR1.FILL0 SaveR7.FILL0.END stored in table, location x21

39. 9-39 TRAP Routines and their Assembler Names vectorsymbolroutine x20GETC read a single character (no echo) x21OUT output a character to the console x22PUTS write a string to the console x23IN print prompt to console, read and echo character from keyboard x25HALT halt the program

40. 9-40 Example LEAR3, Binary LDR6, ASCII; char->digit template LDR7, COUNT; initialize to 10 AGAINTRAPx23; Get char ADDR0, R0, R6; convert to number STRR0, R3, #0; store number ADDR3, R3, #1; incr pointer ADDR7, R7, -1; decr counter BRpAGAIN; more? BRnzpNEXT ASCII.FILLxFFD0 COUNT.FILL#10 Binary.BLKW#10 What’s wrong with this routine?

41. 9-41 Saving and Restoring Registers Must save the value of a register if:  Its value will be destroyed by service routine, and  We will need to use the value after that action. Who saves?  caller of service routine? knows what it needs later, but may not know what gets altered by called routine  called service routine? knows what it alters, but does not know what will be needed later by calling routine

42. 9-42 Saving and Restoring Registers Called routine -- “callee-save”  Before start, save any registers that will be altered (unless altered value is desired by calling program!)  Before return, restore those same registers Calling routine -- “caller-save”  Save registers destroyed by own instructions or by called routines (if known), if values needed later save R7 before TRAP save R0 before TRAP x23 (input character)  Or avoid using those registers altogether Values are saved by storing them in memory.

43. 9-43 Question Can a service routine call another service routine? If so, is there anything special the calling service routine must do?

44. 9-44 What about User Code? Service routines provide three main functions: 1. Shield programmers from system-specific details. 2. Write frequently-used code just once. 3. Protect system resources from malicious/clumsy programmers. Are there any reasons to provide the same functions for non-system (user) code?

45. 9-45 Subroutines A subroutine is a program fragment that:  lives in user space  performs a well-defined task  is invoked (called) by another user program  returns control to the calling program when finished Like a service routine, but not part of the OS  not concerned with protecting hardware resources  no special privilege required Reasons for subroutines:  reuse useful (and debugged!) code without having to keep typing it in  divide task among multiple programmers  use vendor-supplied library of useful routines  Most importantly structure your code

46. 9-46 JSR Instruction Jumps to a location (like a branch but unconditional), and saves current PC (addr of next instruction) in R7.  saving the return address is called “linking”  target address is PC-relative (PC + Sext(IR[10:0]))  bit 11 specifies addressing mode (one opcode, two instructions) if =1, PC-relative: target address = PC + Sext(IR[10:0]) if =0, register: target address = contents of register IR[8:6]

47. 9-47 JSR NOTE: PC has already been incremented during instruction fetch stage.

48. 9-48 JSRR Instruction Just like JSR, except Register addressing mode.  target address is Base Register  bit 11 specifies addressing mode What important feature does JSRR provide that JSR does not?

49. 9-49 JSRR NOTE: PC has already been incremented during instruction fetch stage.

50. 9-50 Returning from a Subroutine RET (JMP R7) gets us back to the calling routine.  just like TRAP

51. 9-51 Example: Negate the value in R0 2sCompNOTR0, R0; flip bits ADDR0, R0, #1; add one RET; return to caller To call from a program (within 1024 instructions): ; need to compute R4 = R1 - R3 ADDR0, R3, #0; copy R3 to R0 JSR2sComp; negate ADDR4, R1, R0; add to R1... Note: Caller should save R0 if we’ll need it later!

52. 9-52 Passing Information to/from Subroutines Arguments  A value passed in to a subroutine is called an argument (or parameter).  This is a value needed by the subroutine to do its job.  Examples: In 2sComp routine, R0 is the number to be negated In OUT service routine, R0 is the character to be printed. In PUTS routine, R0 is address of string to be printed. Return Values  A value passed out of a subroutine is called a return value.  This is the value that you called the subroutine to compute.  Examples: In 2sComp routine, negated value is returned in R0. In GETC service routine, character read from the keyboard is returned in R0.

53. Computer Science 210 s1c Computer Systems 1 2014 Semester 1 Lecture Notes James Goodman (revised by Robert Sheehan) Credits: Slides prepared by Gregory T. Byrd, North Carolina State University More on Subroutines Lecture 15 53

54. 9-54 Using Subroutines In order to use a subroutine, a programmer must know:  its address (or at least a label that will be bound to its address)  its function (what does it do?) NOTE: The programmer does not need to know how the subroutine works, but what changes are visible in the machine’s state after the routine has run.  its arguments (where to pass data in, if any)  its return values (where to get computed data, if any)

55. 9-55 Saving and Restoring Registers Since subroutines are just like service routines, we also need to save and restore registers, if needed. Generally use “callee-save” strategy, except for return values.  Save anything that the subroutine will alter internally that shouldn’t be visible when the subroutine returns.  It’s good practice to restore incoming arguments to their original values (unless overwritten by return value). Remember: You MUST save R7 if you call any other subroutine or service routine (TRAP).  Otherwise, you won’t be able to return to caller.

56. 9-56 Example (1) Write a subroutine FirstChar to: find the first occurrence of a particular character (in R0) in a string (pointed to by R1); return pointer to character or to end of string (NULL) in R2. (2) Use FirstChar to write CountChar, which: counts the number of occurrences of a particular character (in R0) in a string (pointed to by R1); return count in R2. Can write the second subroutine first, without knowing the implementation of FirstChar!

57. 9-57 CountChar Algorithm (using FirstChar) save regs call FirstChar R3 <- M(R2) R3=0 R1 <- R2 + 1 restore regs return no yes save R7, since we’re using JSR

58. 9-58 CountChar Implementation ; CountChar: subroutine to count occurrences of a char CountChar STR3, CCR3; save registers STR4, CCR4 STR7, CCR7; JSR alters R7 STR1, CCR1; save original string ptr ANDR4, R4, #0; initialize count to zero CC1JSRFirstChar; find next occurrence (ptr in R2) LDRR3, R2, #0; see if char or null BRzCC2; if null, no more chars ADDR4, R4, #1; increment count ADDR1, R2, #1; point to next char in string BRnzpCC1 CC2ADDR2, R4, #0; move return val (count) to R2 LDR3, CCR3; restore regs LDR4, CCR4 LDR1, CCR1 LDR7, CCR7 RET; and return

59. 9-59 FirstChar Algorithm save regs R2 <- R1 R3 <- M(R2) R3=0 R3=R0 R2 <- R2 + 1 restore regs return no yes

60. 9-60 FirstChar Implementation ; FirstChar: subroutine to find first occurrence of a char FirstChar STR3, FCR3; save registers STR4, FCR4; save original char NOTR4, R0; negate R0 for comparisons ADDR4, R4, #1 ADDR2, R1, #0; initialize ptr to beginning of string FC1LDRR3, R2, #0; read character BRzFC2; if null, we’re done ADDR3, R3, R4; see if matches input char BRzFC2; if yes, we’re done ADDR2, R2, #1; increment pointer BRnzpFC1 FC2LDR3, FCR3; restore registers LDR4, FCR4; RET; and return

61. 9-61 Library Routines Vendor may provide object files containing useful subroutines  don’t want to provide source code -- intellectual property  assembler/linker must support EXTERNAL symbols (or starting address of routine must be supplied to user)....EXTERNALSQRT... LDR2, SQAddr ; load SQRT addr JSRRR2... SQAddr.FILL SQRT Using JSRR, because we don’t know whether SQRT is within 1024 instructions.