1. Rendszerarchitektúra Sima Dezső 2007 tavaszi félév (Ver. 2.0)  Sima Dezső, 2007

2. Felépítés 1. Introduction to system architectures 2. The evolution of the system architecture 3. The evolution of Intel’s x86 processor bus 4. Bus innovations introduced in intel’s P4 chipsets 5. Chipsets of Intel’s P4 family 6. Bandwidth considerations 7. Special aspects of the implementation

3. 1. Introduction to system architectures

4. System level Processor level Functional unit level Abstract architecture Concrete architecture Figure 1.1.: Interpretation of the notion architecture at different levels 1. Introduction FMUL Pentium Pro Pentium Pro system OS Pentium Pro Processor ISA

5. 2. The evolution of the system architecture

6. ISA-based System architecture of Intel’s desktop PCs Port-based Simple w/ATA, USB w/AGP, ATA,USB PCI-based 8088/80286/ 80386- based PCs 486 and early Pentium based PCs Mature Pentium based PCs Early PII and PIII based PCs Mature PIII/P4 based PCs Intel 420 chipsets Mature Intel 430 chipsets Intel 440XX chipsets Intel 8XX chipsets Evolution Early implem. Recent implem. P4 Prescott based PCs Intel 915X chipsets 2.1 System architecture of Intel’s desktop PCs - Overview

7. 2.2 Main steps of the evolution (1) Figure 2.1: ISA-bus based system architecture (Used typically in 8088/80286/80386-based PCs) 8088/80286/80386 Processor Memory/ Bus controller Main Memory KBD FD Adapter Monitor Adapter WD Adapter PP Adapter SP Adapter ISA Multi-I/O card (DRAM/FPM) I/O devices

8. 2.2 Main steps of the evolution (2) Figure 2.2: S imple PCI-based system architecture (Used typically in 486 and early Pentium-based PCs along with Intel 420 and early 430 chipsets) 486/Pentium System controller PCI bus (Legacy and/or Processor bus L2 cache Main Memory (FPM/EDO) Peripheral controller PCI device adapter ISA device adapter ISA bus slow devices)

9. 2.2 Main steps of the evolution (3) Figure 2.3: PCI-based system architecture with IDE/ATA and USB ports (Used typically in mature Pentium-based PCs with mature Intel 430 chipsets) IDE port: First on the 430FX (Triton, 1995) ATA/33: First on the 430TX (1997) USB: First on the 430VX (Triton III, 1996) Pentium System controller PCI bus (Legacy and/or Processor bus L2 cache Main Memory (FPM/EDO/SDRAM) Peripheral controller PCI device adapter ISA device adapter ISA bus slow devices) USB IDE/(ATA/33)

10. 2.2 Main steps of the evolution (4) Figure 2.4: PCI-based system architecture with AGP, IDE/ATA and USB ports (Used typically in PentiumII and early PentiumIII-based PCs with Intel 440XX chipsets) System controller PCI bus Processor bus Main Memory (EDO/SDRAM) Peripheral controller PCI device adapter ISA device adapter ISA bus PentiumII/ PentiumIII PentiumII/ PentiumIII AGP 2xIDE/ATA33/66 2xUSB (Legacy and/or slow devices)

11. 2.2 Main steps of the evolution (5) Figure 2.5: Early port-based system architecture (Used typically in PentiumIII and Pentium4-based systems with Intel 8X0 chipsets) System controller PCI bus Processor bus Main Memory (SDRAM/) Peripheral controller PCI device adapter ISA device adapter ISA bus PentiumIII/ Pentiu4 AGP 2xIDE/ 2x/4x USB Hub interface ATA 33/66/100 PCI to ISA bridge LPC Super I/O (KBD, MS, FD, SP, PP, IR) AC'97 (Legacy and/or slow devices)

12. 2.2 Main steps of the evolution (6) Figure 2.6: Recent port-based system architecture System controller PCI bus Processor bus Main Memory (SDRAM/) Peripheral controller PCI device adapter Pentium 4 PCI E.x16 1xIDE/ 8x USB Hub interface ATA 33/66/100 LPC (KBD, MS, FD, SP, PP, IR) AC'97 4x SATA PCI E.x1 (1x/2x) LAN 10/100 HDAI

13. 3. The evolution of Intel’s x86 processor bus

14. Figure 3.1 : Main features of the system-bus Main features of the system-bus address bus (bit) data bus (bit) 8086 8088802868038680486Pentium Pentium Pro PII, PIII P4 20 24 32 36 168 32 64 64+8 Multiplexed Bits 0,1 not implemented (Doubleword aligned) Bits 0-2 not implemented (Quadword aligned) 2 3 2 3 2 Width of the 1 4 For error protection 1 1 1 1 4 4

15. 4. Bus innovations introduced into Intel’s P4 chipsets

16. Figure 4.1 : Bus innovations introduced into Intel’s P4 chipsets 4. Bus innovations introduced into Intel’s P4 chipsets (1) PCI PCI-X SATA AGP PCI Express HDAI USB AC' 97 2001200220032004 AC' 97 2.3 USB 2.0 AGP 8x SATA 1.0a PCI 2.3 PCI-X 2.2 PCI Express 1.0a HDAI 11/02 5/03 2/04 6/04 5/02 12/01 6/04

17. Figure 4.2.: Early evolution of the AGP port 4. Bus innovations introduced into Intel’s P4 chipsets (2) Processor bus Memory bridge (North bridge) The principle of the AGP port Frame buffer I/O bridge (South bridge) Graphic chip Main memory AGP (Intel) Version 1.0Version 2.0 (7/1998) (5/1998) (Based on Revision 2.1 of the PCI) 66 MHz Seperate 32-bit address bus and 32-bit data bus Transfer of 8-byte data blocks 1x2x4x Clock speed Bus Transfer mode Transfer rate (Multiplexed 32-bit address bus /data bus) (Transfer of 4-byte data blocks) (PCI) (AGP-66)(AGP-133)(AGP-266) (double clocked) (quadruple clocked) 264 MB/s532 MB/s1064 MB/s Main Features of the AGP port AGP

18. 4. Bus innovations introduced into Intel’s P4 chipsets (3) 1987888990919293941995969798992000010203 ISA 8.33 MHz 8/16-bit EISA 8.33 MHz 32-bit PCI 33 MHz 32-bit PCI v.2 33 MHz 64-bit PCI v.2.1 1 33/66 MHz 32/64-bit PCI v.2.3 2 33/66 MHz 32/64-bit PCI v.2.2 1, 3 33/66 MHz 32/64-bit 1 : Both 3.3 V and 5 V is supported 2 : Only 3.3 V is supported 3 : Just improving the readibility of the standard text Figure 4.3: The evolution of the PCI bus standard

19. 4. Bus innovations introduced into Intel’s P4 chipsets (3) 1987888990919293941995969798992000010203 PCI-X v.1.0 2 66/133 MHz 64-bit PCI-X v.2.0 2 266/533 MHz 64-bit 1 : Both 3.3 V and 5 V is supported 2 : Only 3.3 V is supported 3 : Just improving the readibility of the standard text Figure 4.4: The introduction of the PCI-X ISA 8.33 MHz 8/16-bit EISA 8.33 MHz 32-bit PCI 33 MHz 32-bit PCI v.2 33 MHz 64-bit PCI v.2.1 1 33/66 MHz 32/64-bit PCI v.2.3 2 33/66 MHz 32/64-bit PCI v.2.2 1, 3 33/66 MHz 32/64-bit

20. Source: PCI Technology overview, Febr. 2003, http://www.digi.com/pdf/prd_msc_pcitech.pdf 4. Bus innovations introduced into Intel’s P4 chipsets (5) Figure 4.5: Slot number limitations of the PCI-X bus

21. 4. Bus innovations introduced into Intel’s P4 chipsets (6) PCI Express 1.0 introduced in 7/2002 A link consists of 1x, 2x, 4x, 8x, 12x, 16x or 32x signal pairs (lanes) in each direction. Transfer rate per lane per direction: 2.5 Gbits/s Encoding 10 bits/byte Aggreagate bandwidth per lane (in both directions together): 2 x 2,5 /10 = 0,5 Gbyte/s The PCI Express bus (3GIO)

22. 4. Bus innovations introduced into Intel’s P4 chipsets (7) ATA (PATA) cable ATA/PATA and SATA cables Figure 4.6.: Contrasting ATA/PATA and SATA cables

23. Figure 4. 7.: Early evolution of the AC ’97 bus 4. Bus innovations introduced into Intel’s P4 chipsets (8) AC '97 Version 1.0 Revision 2.1 (9/1997) Version 2.0 Revision 2.2 (5/1998) (9/2000) 6/1996: 5 vendors (Intel, ADI, Creative Labs, National Semiconductor, Yamaha). Link: 5-wire digital (2 serial data lines) Audio Codec 16-bit optionally 18/20-bit AD/DA resolution 48 KHz sampling rate 4 analog stereo inputs 2 analog mono inputs 4/6 channel output dedicated mic input Digital controller May reside on any bus (ISA, PCI, USB, 1394) or in an I/O-bridge High Quality audio (up to 96 KHz sampling rate 120 dB dynamic range) Multiple codec Modem extension (Cost effective) capability (for multichannel audio solutions etc.)

24. 4. Bus innovations introduced into Intel’s P4 chipsets (9) High definition audio (HDA) No. of channels Resolution AC’97 v.2.2 HDAI 6 20-bit Sampling rate 96 kHz 8 32-bit 192 kHz

25. Figure 4. 8 : Peak bandwidth values and sustained data rates of peripheral buses 4. Bus innovations introduced into Intel’s P4 chipsets (10)

26. 5. Chipsets of Intel’s P4 family

27. 5.1 Overview of the P4 family 5.2 Desktop chipsets 5.4 DP server chipsets 5.5 DP workstation chipsets 5.3 Overview of DP server and workstation chipsets

28. Figure 5.1: Intel’s P4 cores (Netburst architecture) 5.1 Overview of the P4 family 4.0/4.2 GHz On-die 1M L2 (Cancelled 5/04) Irwindale-A 11/03 ^ 800 MHz FSB 3.2EE GHz On-die 512K L2, 2M L3 0.13 /178 mtrs  Cores supporting EM64T 6/04 ^ 0.09 /125mtrs  800 MHz FSB 2.8/3.0/3.2/3.4/3.6 GHz On-die 1M L2 11/04 ^ Irwindale-B 0.13 /178mtrs  1066 MHz FSB 3.4EE GHz On-die 512K L2, 2 MB L3 533 MHz FSB 2.4/2.53/2.66/2.8 GHz On-die 256K L2 0.09  6/04 ^ Celeron-D  PGA 603    PGA 604  PGA 478LGA 775  PGA 423  PGA 478     LGA 775 PGA 478   PGA 603  0.18 /42 mtrs  ^ 400 MHz FSB Willamette On-die 256K L2  PGA 478 3/04 ^ Gallatin 0.13 /286 mtrs  400 MHz FSB 2.2/2.7/3.0 GHz On-die 512K L2 On-die 2M/4M L3  PGA 603 8/01  PGA 478  533 MHz FSB 2.53/2.66/2.80/2.93 GHz On-die 256K L2 0.09  9/04 ^ Celeron-D Extreme Edition 7/03 ^ Prestonia-C 0.13 /178 mtrs  533 MHz FSB 3.06 GHz On-die 512K L2, 1M L3  PGA 603 1.4... 2.0 GHz 0.09 /125mtrs  800 MHz FSB 3.20F/3.40F/3.60F GHz On-die 1M L2 LGA 775 8/04 ^ 1213 8,9,10 Prescott Prescott-F 11 5 6,7 LGA 775 42,3 1 1

29. Figure 5.2: Intel’s chipsets designed for P4-based value and desktop PCs Chipsets 5/02 4/03 5/03 10/02 6/04 8/03 5/03 9/03 5/03 9/036/04 FSB Willamette 400 MHz 533 MHz 11/00 HT Socket Cores EM64T Northwood-A Northwood-B Willamette 11/02 5/02 1/02 8/01 HT 400 MHz EM64T PGA 423  PGA 478     Northwood-C 800 MHz 5/03 HT Prescott 6/04 2/04 800 MHz HT PGA 478   LGA 775 Prescott F 8/04 Northwood-B 845 G/E/GL 865P 845GV/GE/PE 848P 865G/GV/PE 875P 915G/GV/P 5.2 Desktop chipsets (1) 9/01 845 11/01

30. Figure 5.3: The evolution of Intel’s chipset families designed for P4-based value/mainstream desktops 5.2 Desktop chipsets (2) 4/0306/04 FSB up to Memory DRAM speed up to Additional high speed SATA PCI USB 845xx family848P 865xx/875P family 915xx family (Brookdale)(Springdale/Canterwood) 533 MT/s800 MT/s Single channel Dual channel SDR/DDR SDRAMDDR SDRAM DDR2 /DDR SDRAM DDR 333DDR 400 DDR 400/DDR2 533 CSA SATA 1.0a PCI 2.2PCI 2.3 USB 2.0 5/02 no HT/HTHT PCI 2.3 8/035/03 (Grantsdale) HT support Nr. of mem. channels (unbuffered) LAN 10/100 Mbit/s PCI Express x1 AC' 97 AC' 97 2.3 (unbuffered) MCH/GMCH 10/100 Mbit/s HDAI 1 PCI Express x1 1.0a 2 3 1 2 3 The Communications Streaming Architecture (CSA) interface of the MCH provides a link to a Gigabit Ethernet Controller (GbE), e.g. to Intel's 82547EI GbE controller The Intel High Definition Audio Interface (HDAI) shares pins with the AC '97 link, so these interfaces cannot be operated concurrently 3 A GbE controller can be attached via the PCI Express x1 link providing 10/100/1000 Mbit/s speeds. (e.g. Intel's 82571EB dual channel GbE controller) Max. memory 2 GB 4 GB interface 845 400 MT/s Single channel SDR/DDR SDRAM DDR 266 PCI 2.2 USB 1.1 9/01 no HT (unbuffered) 10/100 Mbit/s AC' 97 2.1 2 GB 11/05 975x 1066 MT/s Dual channel DDR2 SDRAM DDR2 667 SATA 1.0a USB 2.0 HT PCI 2.3 (unbuffered) AC' 97 2.3 ICH ICH4:ICH5/ICH5R: ICH6/ICH6R: Graphics interface up to AGP 4XAGP 8X PCI Express x16 ICH2: AGP 4X ICH7/ICH7R: PCI Express x16 10/100 Mbit/s HDAI PCI Express x1 1.0a 2 8 GB ATA up to Ultra ATA/100

31. Figure 5.4: The evolution of chipsets intended primarily for P4-based value/mainstream desktops P4 ICH ICH2/4/5/5R /6/6R BIOS MCH SDRAM interface SDRAM interface PC 133, DDR 200/266/333/400, DDR2 400/533 unbuffered, ECC opt. 3 3 The 865xx, 865 and 915xx chipsets have a dual channel memory link.. FSB FWH ATA/100 SATA LAN 10/100 GPI0 LPC PCI PCI-X PCI Express x1 USB AC/97 HDAI Max. 2/4 GB HI 1.5/DMI (845/845xx/848P/865xx/ 875P/915xx) AGP 4X/8X/PCI Express x.16 3 4 4 The 845 has a max. memory of 3 GB for SDR SDRAMs. 5 6 5 ICH4 ICH5(R) ICH6(R) 4 6x v2.2 6x v2.37x v2.3 6x v2.0 8x v2.0 v2.3 ICH2 6x v2.2 4x v1.1 v2.1 845xx848P 845 865xx 915xx 875P 5 6 6 VGA 1 2 1 The chipsets including the letter G in their designation provide an integrated graphics controller. 2 The chipsets including the letters GL or GV in their designation don't have an AGP or PCI Express x16 interface. The ICH5R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation. The ICH6R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation. ICH4ICH5(R)ICH6(R) 2 1 2 4 2 845xx848P 845 865xx 915xx ICH2 2 875P 5 6 5 6 5.2 Desktop chipsets (4)

32. Figure 5.5: Main features of Intel’s I/O Control Hubs (ICH) used in P4-based chipsets 5.2 Desktop chipsets (3)

33. Figure 5.6: Intel’s chipsets designed for P4-based value and desktop PCs Chipsets 9/01 5/02 4/03 5/03 10/02 6/04 8/03 5/03 9/03 5/03 9/036/04 FSB Willamette 400 MHz 533 MHz 11/00 HT Socket Cores EM64T Northwood-A Northwood-B Willamette 11/02 5/02 1/02 8/01 HT 400 MHz EM64T PGA 423  PGA 478     Northwood-C 800 MHz 5/03 HT Prescott 6/04 2/04 800 MHz HT PGA 478   LGA 775 Prescott F 8/04 Northwood-B 845 845 G/E/GL 865P 845GV/GE/PE 848P 865G/GV/PE 875P 915G/GV/P 5.2 Desktop chipsets (1) 845 11/01

34. Figure 5.7: Main features of Intel’s 845xx family of chipsets 5/0210/02 Graphics interface up to 845GL845GV 845G845E 845GE IG 400 MHz 533/400 MHz AGP 4X IG 10/02 845xx family (Brookdale) 10/100 Mbit/s Ultra ATA/100 PCI 2.2 Single channel SDR/DDR SDRAM AGP 4X 5/02 FSB HT not supportedHT supported 845 AGP 4X IG 5/02 10/02 845PE AGP 8X PC133, DDR 266/200 DDR 333/266 Integrated graphics (IG) AGP 4X 9/01 12/01 PC133 PC133, DDR 266/200 PC133, DDR 266/200 Memory protection ECC (opt.) (unbuffered) HT support DRAM speed ICH ICH4: ICH2: ICH4: ICH2: USB USB 2.0USB 1.1 ICH4: USB 2.0 Features Memory ATA up to PCI LAN AC '97AC '97 2.3AC '97 2.1 AC '97 2.3 MCH/GMCH AC '97 2.3 Target line at introduction Target core at introduction P4 Celeron/P4P4 Celeron/P4 Willamette Willamette-128/ Northwood-A Northwood-B with HT Northwood-B with HT Northwood-128/ Northwood-B with HT   PGA 478   PGA 478   1 2 The 845 has a max. memory of 2 GB for DDR SDRAMs and 3 GB for SDR SDRAMs. Max. memory 2 GB 1 2 At introduction of the 845G and 845E chipsets (5/02) Intel did not made any notice about supporting hyperthreading. But in 10/02 Intel revealed that the enhanced 845G (B stepping) and the original 845E do support hyperthreading with upgraded BIOSs. 5.2 Desktop chipsets (5) 11/01 845

35. Figure 5.8: Typical configuration of a value/desktop motherboard based on Intel’s 845xx family of chipsets 5.2 Desktop chipsets (6) ICH4 FWH SDRAM interface DDR 200/266/333 unbuffered, no ECC Audio GPIO FSB LPC HI 1.5 P4 Northwood 845xx 400/533 MHz Max. 2 GB GbE c. LAN 10/100 GbE PCI v.2.2 SIO FDKBMSSPPP (3-6 slots) MbE c. MbE USB 2.0 (4-6 ports) CODEC AC'97 v.2.3 AGP 4x VGA (G)MCH 1 1,2 1 2 The chipsets including the letter G in their designation provide an integrated VGA controller. Mainboards based on the 845 chipset have a different configuration since they work with the ICH2. 3 Ultra ATA/100 (2 ports) PCI v.2.2 3 The chipsets 845GL/GV don't offer an AGP interface.

36. Figure 5.9: Intel’s chipsets designed for P4-based value and desktop PCs Chipsets 5/02 4/03 5/03 10/02 6/04 8/03 5/03 9/03 5/03 9/036/04 FSB Willamette 400 MHz 533 MHz 11/00 HT Socket Cores EM64T Northwood-A Northwood-B Willamette 11/02 5/02 1/02 8/01 HT 400 MHz EM64T PGA 423  PGA 478     Northwood-C 800 MHz 5/03 HT Prescott 6/04 2/04 800 MHz HT PGA 478   LGA 775 Prescott F 8/04 Northwood-B 845 G/E/GL 865P 845GV/GE/PE 848P 865G/GV/PE 875P 915G/GV/P 5.2 Desktop chipsets (1) 9/01 845 11/01

37. Figures 5.10: Main features of Intel’s 915xx family of chipsets 5.2 Desktop chipsets (7) 6/04 FSB DRAM speed Integrated graphics (IG) Graphics interface up to 910GL915P915G915GV (Grantsdale-G) 533 MHz 800/533 MHz DDR 400/333 DDR2 533/400, DDR 400/333 PCI Express x16 (Grantsdale-P) IG 6/04 915xx family PCI 2.3 Ultra ATA/100 PCI Express x1 1.0a HT supported IG 9/04 Dual channel DDR2/DDR SDRAM (unbuffered, no ECC) 4 4 Supports processors also in socket PGA 478.  ICH6: Features HT support Memory ICH IDE up to PCI Express PCI MCH/GMCH SATA SATA 1.0a LAN AC '97 HDAI 10/100 Mbit/s AC '97 2.3 HDAI supported (Grantsdale-V)(Grantsdale-GL) 2 2 A GbE controller can be attached via the PCI Express x1 link providing 10/100/1000 Mbit/s speeds (e.g. Intel's 82571EB dual channel GbE controller). 3 3 3 The Intel High Definition Audio Interface (HDAI) shares pins with the AC '97 link, so these interfaces cannot be operated concurrently. Target line at introduction Target core at introduction Celeron /P4 Celeron Celeron D Celeron D/Prescott without EM64T  LGA 775   PGA 478/LGA 775 (Grantsdale) 1 Max. memory4 GB The max. memory of the 910GL is restricted only to 2 GB. 1

38. Figure 5.11: Typical configuration of a value/desktop motherboard based on Intel’s 915xx family of chipsets 5.2 Desktop chipsets (8) 1 2 The chipsets including the letter G in their designation provide an integrated VGA controller. The 915GL/GV chipsets don't offer a PCI Express x16 interface. ICH6 FWH SDRAM interface SDRAM interface DDR 333/400, DDR2 400/533 unbuffered, no ECC Ultra ATA/100 PCI E. x1 Audio GPIO FSB LPC DMI P4 Prescott 915xx 533/800 MHz Max. 4 GB PCI E. x16 MbE c. LAN 10/100 PCI E. x1 MbE PCI v.2.3 SIO FDKBMSSPPP (1-2 ports) (2-4 slots) GbE c. GbE USB 2.0 (8 ports) CODEC AC'97 v.2.3 SATA (4 ports) PCI E. x16 VGA (G)MCH 1 1 2 PCI v.2.3 (1 port)

39. Figure 5.12: Intel’s chipsets designed for P4-based DP-servers and workstations 5.3 Overview of DP server and workstation chipsets FSB DP-servers Foster 400 MHz 533 MHz 800 MHz 5/01 HT Socket Cores EM64T Prestonia-B Prestonia-C Nocona Prestonia-A 6/047/0311/022/02 HT 533 MHz HT EM64T PGA 603     PGA 604  Chipsets DP-workstations 5/01 2/02 8/04 11/02 6/04 860 E7500 E7501 E7505 E7320 E7520 E7525

40. Figure 5.13: The evolution of Intel’s chipsets designed for P4 Xeon-based dual processor (DP) servers and workstations (WS) 5.4 DP server chipsets (1) 11/02 8/04 Graphics interface up to PCI PCI-X E7500E7320 E7501 E7505 E7520 (Plumas) 400 MHz 533 MHz 800 MHz 1x PCI Express x8 PCI 2.2 (Lindenhurst-VS)(Lindenhurst) 8/04 E75xx/E73xx family (registered, ECC) Dual channel SDRAM HT supported AGP 8X 2/02 11/02 DDR 266 /200 DDR 200 DDR 333/266 6/04 E7525 DDR 333 (Tumwater) (Placer) Aim DP server DP WSDP server DP WS 3x PCI Express x8 PCI Express x16 PCI 2.2 PCI 2.3/PCI 2.2 1 The 7505 supports also unbuffered DDR SDRAMs. FSB SATASATA 1.0a Features HT support IDE up to EM64T supported EM64T support DRAM speed ICH ICH3-S: ICH4: ICH5R:/6300ESB: PCI Express x1 AC' 97 AC '97 2.2 USBUSB 1.1 USB 2.0 LAN 10/100 Mbit/s /PCI-X 2.2 PCI 2.3/PCI 2.2 AC '97 2.3AC '97 2.2AC '97 2.2/AC '97 2.3 10/100 Mbit/s MCH RAS/RASUM RASUM RASRASUM 400 MHz AGP 4X PCI 2.2 5/01 PC 800/600 DP WS ICH2: AC '97 2.1 USB 1.1 10/100 Mbit/s 860 ECC (opt.) RDRAM Dual channel DDR2 400 Target cores at introduction Foster Prestonia-A Prestonia-B Nocona Technology/Socket PGA 603  2 2 The 7520 includes an integrated four channel DMA engine in contrast to the E7320. PGA 603PGA 604 Nr. of mem. channels Memory Memory protection Ultra ATA/100  3x HI 2.0 Additional high speed if. 3 4 Max. memory4 GB16 GB 1 1x PCI Express x8 1x HI 2.0 4 2x HI 3 3 3 4 The ICH5R incorporates a RAID controller (Redundant Arrays of Indepentdent Disks) that utilizes the dual SATA ports for a high-performance RAID Level 0 configuration. Reliability, Availability, Serviceability, Usability, Manageability 1 4 4 4 4 4 4

41. Figure 5.14: The evolution of DP-server chipsets of P4 cores 5.4 DP server chipsets (2) 1 The 16-bit HI 2.0 link is used to add PCI/PCI-X bridges (6700PXH), while the PCI Express x8 links are usually configured as two independent x4 ports, each providing the possibility to add a PCI/PCI-X brigde (e.g. 6700PXH) or a dual GbE controller 2 Reliability, Availability, Serviceability, Usability, Manageability 3 The E7320 has only a single PCI Express x8 high speed interface 5 The ICH5R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation 4 An external SATA controller is needed only in connection with the ICH3-S 6 The 6300ESB SATA supports soft RAID. P4 ICH (ICH3-S/5R /6300ESB) BIOS MCH SDRAM interface SDRAM interface DDR 200/266/333/400, DDR2 400 registered, ECC 1 FSB FWH HI 1.5 P4 (E7500/7501/7320 /7520) with RASUM 2 HI 2.0/PCI E. x8 5 SATA ATA/100 LAN 10/100 GPI0 LPC PCI PCI-X PCI Express x1 USB AC' 97 HDAI Max. 8-32 GB 3 High speed if. Xeon ICH3-SICH5R6300ESB 2 2 2 22 E7500 E7501 E7520E3520 5 65 6 ICH3-SICH5R6300ESB 4x v.2.2 6x v2.26x v2.34x v2.2 6x v1.1 8x v2.0 4x v2.0 E7500 E7501 E7520 E7320 v2.2 v2.3 v2.2 5 6

42. Figure 5.15: Typical configuration of a DP-server motherboard based on Intel’s E7500/E7501 chipsets 5.4 DP server chipsets (3) P4 ICH3-S FWH E7500/E7501 SDRAM interface SDRAM interface DDR 200/266 registered, ECC opt. Ultra ATA/100 PCI v.2.2 USB v. 1.1 GPIO FSB LPC HI 1.5 P4 (with RASUM) HI 2.0 PCI-X v.2.2 Prestonia MCH 400/533 MHz 8/12/16 GB HI 2.0 PCI-X bridge SATA c. GbE c. PCI-X v.2.2 SATA GbE Video c. MbE c. PCI v.2.2 (5 ports) SVGA MbE SIO FDKBMSSPPP SCSI c. SCSI (1-2 slots) (3 slots) (2 ports)

43. Figure 5.16: Typical configuration of a DP-server motherboard based on Intel’s E7520 chipset (including the ICH5R) 5.4 DP server chipsets (4) P4 ICH5R FWH E7520 SDRAM SDRAM SDRAM interface SDRAM interface DDR 266/333, DDR2 400 registered, ECC opt. Ultra ATA/100 PCI v.2.3 USB v. 2.0 SATA AC' 97 v.2.3 GPIO FSB LPC HI 1.5 P4 (with RASUM) PCI E. x8 PCI-X v.1.0b Nocona Nocona MCH 800 MHz 16/24/32 GB PCI E. x8 PCI-X bridge SCSI c. GbE c. PCI-X v.1.0b PCI E. x8 (or 2x x4) SCSI GbE Video c. PCI v.2.3 (4 ports) SVGA SIO FDKBMSSPPP (2 ports) (1 slot) (1-2 slot) (0-1 slot)

44. Figure 5.17: The evolution of DP-workstation chipsets of P4 cores 5.5 DP workstation chipsets (1) P4 ICH (ICH2/4/5R/6300ESB) BIOS MCH SDRAM interface SDRAM interface DDR 200/266/333, DDR2 400 registered, ECC opt. 1 1 The first chipsets of this line (the 860) worked with DRDRAMs while using PC 600/800. FSB FWH HI 1.5 P4 (860 /E7505/7525) with RASUM 2 AGP 4X/8X/PCI E. x16 2 Reliability, Availability, Serviceability, Usability, Manageability 3 The MCH of the 860 provides two 16-bit high speed interfaces, to add PCI v2.2 bridges (P64H). The ICH5R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation 4 SATA ATA LAN 10/100 GPI0 LPC PCI PCI-X PCI Express x1 USB AC' 97 HDAI 2,3 Xeon Max. 16 GB ICH4 ICH5R6300ESB 2 2 2 22 E7505 4 54 ICH2 2 860E7525 5 ICH4ICH5R 6300ESB 4x v.2.2 6x v2.26x v2.3 4x v2.2 6x v2.0 8x v2.04x v2.0 v2.3 v2.2 6x v2.2 4x v1.1 v2.1 ICH2 E7505860E7525 45 The 6300ESB SATA supports soft RAID. 5 HI 2.0, PCI E x8 PCI-X bridge SCSI SATA GbE

45. Figure 5.18: Typical configuration of a DP-workstation motherboard based on Intel’s E7505 chipset 5.5 DP workstation chipsets (2) P4 FWH E7505 SDRAM interface SDRAM interface DDR 200/266 registered, ECC opt. Ultra ATA/100 GPIO FSB LPC HI 1.5 P4 (with RASUM) Prestonia B/C MCH 533 MHz 8/12 GB AGP 8x SIO FDKBMSSPPP ICH4 Audio MbE c. PCI v.2.2 MbE PCI v.2.2 USB 2.0 (4 ports) CODEC AC'97 v.2.2 Prestonia B/C PCI-X v.2.2 HI 2.0 PCI-X SATA c. GbE c. PCI-X v.2.2 SATA GbE SCSI c. SCSI (1-2 slots) bridge (2 ports) (1-2 slots)

46. Figure 5.19: Typical configuration of a DP-workstation motherboard based on Intel’s E7525 chipset 5.5 DP workstation chipsets (3) P4 6300ESB FWH E7525 SDRAM interface SDRAM interface DDR 266/330 registered, ECC opt. Ultra ATA/100 GPIO FSB LPC HI 1.5 P4 (with RASUM) PCI E. x16 Nocona MCH 800 MHz 16/24/32 GB PCI E. x8 SIO FDKBMSSPPP ICH SATA PCI-X v.2.2 Audio GbE c. PCI-X v.2.2 GbE PCI v.2.2 USB 2.0 (4 ports) CODEC AC'97 v.2.2 (2 ports) PCI-X GbE c. PCI-X GbE c. bridge (2 slots) x4 (1-2 slots)

47. Source: Intel.com/products/I/chipsets/975x 5.6 Intel’s 975X chipset Figure 5.20: Intel’s 975X chipset for dual core processors

48. 6. Bandwidth considerations

49. Figure 6.1: Main features of the FSB and SDRAM interfaces 6. Bandwidth considerations (1) FSB SDRAM-interface WidthPeak aggregate bandwidth 64-bit8 * f Mbyte/s c 64-bit8 * f Mbyte/s SDRAM

50. Figure 6.2: Main features of MCH/ICH interfaces used in Intel’s P4-based chipsets 6. Bandwidth considerations (2)

51. Figure 6.3: Main features of high speed MCH interfaces of Intel’s P4-based chipsets 6. Bandwidth considerations (3)

52. Figure 6.4: Peak bandwidth values (Mbyte/s) in typical desktops, based on Intel’s 865xx chipsets 6. Bandwidth considerations (4)

53. Figure 6.5: Peak bandwidth values (Mbyte/s) in typical desktops, based on Intel’s 915xx chipsets ICH6 FWH SDRAM interface SDRAM interface DDR 333/400, DDR2 400/533 unbuffered, no ECC Ultra ATA/100 PCI E. x1 Audio GPIO FSB LPC DMI P4 Prescott 915xx 533/800 MHz 4 GB PCI E. x16 MbE c. PCI v.2.3 PCI E. x1 MbE PCI v.2.3 SIO FDKBMSSPPP (1-2 ports) (2-4 slots) GbE c. GbE USB 2.0 (8 ports) CODEC AC'97 v.2.3 SATA (4 ports) PCI E. x16 VGA (G)MCH 1 8000 3200-6400 2664- 4264 2664- 4264 133 1.4 1*100 4*150 ~5 500 60 8000 2000 (1 ports) 6. Bandwidth considerations (5)

54. Figure 6.6: Peak bandwidth values (Mbyte/s) in typical DP-servers, based on Intel’s E7500/E7501 chipsets 6. Bandwidth considerations (6) P4 ICH3-S FWH E7500/E7501 SDRAM interface SDRAM interface DDR 200/266 registered, ECC opt. Ultra ATA/100 PCI v.2.2 USB v. 1.1 GPIO FSB LPC HI 1.5 P4 (with RASUM) HI 2.0 PCI-X v.2.2 Prestonia MCH 400/533 MHz 8/12/16 GB HI 2.0 PCI-X bridge SATA c. GbE c. PCI-X v.2.2 SATA GbE Video c. MbE c. PCI v.2.2 LAN (5 ports) SVGA MbE SIO FDKBMSSPPP SCSI c. SCSI (1-2 slots) (3 slots) 3200-4264 1600- 2128 1600- 2128 266 133 1.5 2*100 ~5 1066 (2 ports)

55. Figure 6.7: Peak bandwidth values (Mbyte/s) in typical DP-servers, based on Intel’s E7520/ICH5R chipset 6. Bandwidth considerations (7) P4 ICH5R FWH E7520 SDRAM interface SDRAM interface DDR 266/333, DDR2 400 registered, ECC opt. Ultra ATA/100 PCI v.2.3 USB v. 2.0 SATA AC' 97 v.2.3 GPIO FSB LPC HI 1.5 P4 (with RASUM) PCI E. x8 PCI-X v.1.0b Nocona MCH 800 MHz 16/24/32 GB PCI E. x8 PCI-X bridge SCSI c. GbE c. PCI-X v.1.0b PCI E. x8 (or 2x x4) SCSI GbE Video c. MbE c. PCI v.2.3 LAN (4 ports) SVGA MbE SIO FDKBMSSPPP 60 3200 2128- 3200 2128- 3200 266133 ~1.4 2*100 2*150 ~5 4000 (2 ports)

56. Figure 6.8: Peak bandwidth values (Mbyte/s) in typical DP-workstations, based on the Intel’s E7505 chipset 6. Bandwidth considerations (8) P4 FWH E7505 SDRAM interface SDRAM interface DDR 200/266 registered, ECC opt. Ultra ATA/100 GPIO FSB LPC HI 1.5 P4 (with RASUM) Prestonia B/C MCH 533 MHz 8/12 GB AGP 8x SIO FDKBMSSPPP ICH4 Audio GbE c. PCI v.2.2 GbE PCI v.2.2 USB 2.0 (4 ports) CODEC AC'97 v.2.2 Prestonia B/C PCI-X v.2.2 HI 2.0 PCI-X SATA c. GbE c. PCI-X v.2.2 SATA GbE SCSI c. SCSI (1-2 slots) bridge 2132 133 4264 1600- 2132 1600- 2132 266 60 1.42*100 ~5 1066 (2 ports)

57. Figure 6.9: Peak bandwidth values (Mbyte/s) in typical DP-workstations based on the Intel’s E7525 chipset 6. Bandwidth considerations (9) P4 6300ESB FWH E7525 SDRAM interface SDRAM interface DDR 266/333 registered, ECC opt. Ultra ATA/100 GPIO FSB LPC HI 1.5 P4 (with RASUM) PCI E. x16 Nocona MCH 800 MHz 16/24/32 GB PCI E. x8 SIO FDKBMSSPPP ICH SATA PCI-X v.2.2 Audio GbE c. PCI-X v.2.2 GbE PCI v.2.2 USB 2.0 (4 ports) CODEC AC'97 v.2.2 8000 4000 3.2-6.4 2132- 2664 2132- 2664 266 133 1.42*100 2*150 ~5 60 533 (2 ports)

58. 7. Special aspects of the implementation

59. 7.1 Attaching the display 7.5 Implementation of ICHs 7.4 Attaching SCSI controllers 7.3 Attaching MbE/GbE controllers 7.2 PCI-X bridges 7. Special aspects of the implementation

60. 7.1 Attaching the display Figure 7.1: Alternatives for attaching a display in P4-based motherboards Typical use: P4 MCH ICH VGA Value/mainstream desktops with the letter G in their designation (e.g. 845G/GL/GV) Entry level servers based on the E7221 P4 Off-board MCH ICH AGP 4x/8x/ PCI E. x8/x16 video c. VGA Value/mainstream desktops excluding those with the letters GL or GV in their designation High end desktops/entry level workstations DP-workstations (e.g. 845GL/GV) P4 MCH ICH PCI 32 bit/33 MHz video c. VGA (mostly ATI Rage XL) Entry level servers based on the E7210 DP-servers On-board

61. Figure 7.2: Use of PCI-X bridges to attach dedicated controllers 7.2 PCI-X bridges (1) PCI-X SATA c. GbE c. SATA GbE SCSI c. SCSI bridge PCI-X HI/HI2.0/PCI E.

62. Figure 7.3: PCI-X bridges used in Intel’s P4-based motherboards 7.2 PCI-X bridges (2) P64H 16 HIPCI 32/64-bit 33/66 MHz 64 (82806AA) P64H2 16 HI 2.0 PCI 2.2/PCI-X 1.0 64 (82870P2) PXH-V 1/4/8 PCI E. 1.0a x1/x4/x8 64 (6702PXH) PXH 64 (6700PXH) PCI E. 1.0a x4/x8 1/4/8 64 PCI 2.3/PCI-X 1.0b 1 64 1 PCI 2.3/PCI-X 1.0b 1 4/8 Used in e.g. 860 E7500/7501/7505 E7221 E7320/7520/7525 1 2 2 2 The interface can be independently configured as either a PCI bus or a PCI-X bus running at 33/66 or 66/100/133 MHz resp. The bridge can operate either in x4 or x8 mode. PCI 2.3/PCI-X 1.0b 1

63. Figure 7.4: Alternatives used to attach a MbE controller in Intel’s P4-based motherboards 7.3 Attaching MbE/GbE controllers (1) 1 2 Examples 82550PM 82551QM E7500/7501/7505 E7500/7501 E7210 MCH ICH MbE c. PCI HI 1.5 2 2 3 82562ET 845xx (opt. MCH ICH MbE c. P4 82562EZ 848P 865xx 875P 915xx HI 1.5 LAN 10/100 1 3 3 3 4 4 The LAN 10/100 interface is also designated as the LCI interface (LAN Connect Interface). The 82550PM or the 8255IQM is available in DP servers and workstations usually in addition to a GbE c. As an exception some early E7500 based motherboards provide only one or two MbE controllers. Most of the enlisted motherboards provide either a MbE controller attached to the LAN 10/100 interface or a GbE controller attached to the CSA interface. A few 915xx based Intel motherboards provide either a 82562EZ MbE controller or the Marvell 88E8050 PCI Express x1-based GbE controller. P4 Value/mainstream desktopsEarly DP servers/workstations (Furthermore E7210) or standard)

64. Figure 7.5: Widely used alternatives to attach a GbE controller in Intel ’ s P4-based motherboards via legacy buses 7.3 Attaching MbE/GbE controllers (2) Examples 82540EM 82541GI 82541PI 845xx E7501 875P 915xx 925X E7210 E7221 MCH ICH PCI-X GbE c. GbE brigde P4 HI 2.0 HI 1.5 82545EM 82546EB (D) E7500/7501/7505 P4 MCH ICH GbE c. PCI GbE HI 1.5 E7205 E7520(w/ICH5R) P4 MCH ICH GbE c. CSA GbE HI 1.5 82547EI 848P 865xx 875P E7210 875P 82547GI 1 1 2 3 5 4 5 4 4 4 Ususally in companion with a MbE controller such as the 82550PM or the 82551QM. Ususally in companion with a MbE controller such as the 82551QM. The 82541PI and the 8254GB is used in the 32-bit/33 MHz mode. The 82541GI is used either in 32-bit/33MHz or 32-bit/66 MHz mode. Most of the enlisted motherboards provide either a MbE controller attached to the LAN 10/100 interface or a GbE controller attached to the CSA interface. 82541GI P4 MCH ICH GbE c. PCI-X GbE P4 (6300ESB) HI 1.5 Advanced DP servers/workstations E7320/7525 (w/6300ESB) 82541GB E7320/7525 (w/6300ESB) 82541PI E7320/7525 (w/6300ESB) 2 3 3 Early DP servers/workstations All categories Mainstream desktops (Furthermore the E7210)

65. 7.3 Attaching MbE/GbE controllers (3) Figure 7.6: Alternatives used to attach a GbE controller inIntel ’ s P4-based motherboards via the PCI Express bus Examples 82570EI (BCM5721 ) 915GV E7221 MCH ICH P4 MCH ICH GbE c. PCI E. x1 P4 82546GB (D) E7520/E7525 (w/ICH5R) HI 1.5 DMI 1 2 2 1 3 3 Used to date (2/05) in Commel's FS-979 motherboards. From Marvell From Broadcom GbE c. (ICH6/ ICH6R) (88E8050 )925X P4 PCI-X PCI E. x8 (ICH5R) x4 MCH ICH P4 82571EB E7320 E7520 E7525 HI 1.5 P4 GbE c. GbE PCI E. x8 (ICH5/ 6300ESB) x4 GbE c. GbE bridge PCI-X Advanced DP servers/workstations Advanced single processor motherboardsAdvanced DP servers/workstations

66. Figure 7.7: Alternatives used to attach a SCSI controller in Intel’s P4-based motherboards Remark: A few entry-level servers and DP-workstations incorporate also a SCSI controller, like some based on the E7221 or E7505 chipsets 7.4 Attaching SCSI controllers Typical use: MCH ICH PCI-X P4 Adaptec A16-7899W P4 MCH ICH P4 MCH ICH (Ultra 160, dual channel) (Ultra 320, single channel) (Ultra 320, dual channel) LSI Logic 53C1020 (Ultra 320, single channel) Adaptec AIC-7902 LSI Logic 53C1030 P4 HI 2.0 PCI-X bridge SCSI c. (P64H2) (E7500/7501) PCI-X bridge SCSI c. (PXH-V) x8 (E7320) PCI-X bridge SCSI c. (PXH) PCI E. x8 (E7520) Advanced high-end DP-servers Early DP-servers Advanced mid-range DP-servers Adaptec AIC-7901 Adaptec AIC-7902 (Ultra 320, dual channel) FSB

67. 7.5 Implementation of ICHs (1) Figure 7.8: Simplified structure of the ICH4 to (G)MCH HI 1.5 8-bit/66 MHz*4 Multiplexer D:8, F0 32-bit/33 MHz LAN 10/100 D:29, F0 USB UHCI c. #1 D:29, F1 USB UHCI c. #2 D:29, F2 USB UHCI c. #3 D:29, F7 USB 2.0 EHCI c. D:30, F0 PCI HUB/PCI bridge D:31, F0 LPC LPC bridge D:31, F1 ATA ATA c. D:31, F3 SMBus USB 2.0 (2 ports) USB 2.0 (2 ports) USB 2.0 (2 ports) (2 port) ICH4 D: Device F: Function UHCI: Universal Host Controller Interface EHCI: Enhanced Host Controller Interface LAN 10/100 (6 master) D:31, F5 AC'97 Audio c. D:31, F6 AC'97 v. 2.3 AC'97 0 Modem c. PCI Bus 1 32-bit/33 MHz PCI Bus 0

68. 7.5 Implementation of ICHs (2) Figure 7.9: Simplified structure of the ICH6 to (G)MCH DMI 4*1-bit/2.5 GHz Multiplexer D8, F0 PCI Bus 1 32-bit/33 MHz LAN 10/100 D27, F0 IHDA/AC'97 v.2.3 IHDA/AC'97 c. D28, F0 PCI E. X1 v1.0a PCI E. port 1 D28, F1 PCI E. x1 v1.0a PCI E. port 2 D28, F2 PCI E. x1 v1.0a PCI E. port 3 D28, F3 PCI E. x1. v1.0a PCI E. port 4 D29, F0 USB 2.0 USB UHCI c. D29, F1 USB UHCI c. D29, F2 USB UHCI c. D29, F3 USB UHCI c. D29, F7 USB 2.0 EHCI c. D30, F0 PCI v.2.3 PCI to PCI bridge D30, F2 AC'97 Audio c. D30, F3 AC'97/IHDA AC'97 Modem c. D31, F0 LPC LPC c. D31, F1 ATA ATA c. D31, F2 SATA SATA c. D31, F3 SMBus SMBus c. (2 ports) USB 2.0 (2 ports) USB 2.0 (2 ports) USB 2.0 (2 ports) (1 port) (4 port) ICH6 D: Device F: Function UHCI: Universal Host Controller Interface EHCI: Enhanced Host Controller Interface LAN 10/100 PCI Bus 0 32-bit/33 MHz