1. Computer Organization CS224
Fall 2012
“Welcome to our course”
Will Sawyer & Fazlı Can
With thanks to M.J. Irwin, D. Patterson, and J. Hennessy for some lecture slide contents

2. CS224 Course Contents
Overview of computer technologies, instruction set architecture (ISA), ISA design considerations, RISC vs. CISC, assembly and machine language, translation and program start-up.
Computer arithmetic, arithmetic logic unit, floating-point numbers and their arithmetic implementations.
Processor design, data path and control implementation, pipelining, hazards, pipelined processor design, hazard detection and forwarding, branch prediction and exception handling.
Memory hierarchy, principles, structure, and performance of caches, virtual memory, segmentation and paging.
I/O devices, I/O performance, interfacing I/O.
Intro to multiprocessors, multicores, and cluster computing.

3. CS224 Policies Everything is on the Web site:
CS Dept > Course Home Pages > CS224
Numerical average will be calculated from:
6 Problem Sets 10%
2 Projects %
Midterm 25%
Final exam 35%
TO PASS, you must:
have exam average > 40% (weighted average)
not drop out (FX) : attend class sometimes, do projects & exams
have overall course performance that is passing
CS224 Spring 2012

4. Computer Organization & Design by Patterson & Hennessy
Why learn this stuff?
You want to call yourself a “computer engineer”
You want to build software people use (need performance)
You need to make a purchasing decision or offer “expert” advice
Both Hardware and Software affect performance:
Algorithm determines number of source-level statements
Language/Compiler/Architecture determine machine instructions (Chapter 2 and 3)
Processor/Memory determine how fast instructions are executed (Chapter 4 and 5)
I/O and Number_of_Cores determine overall system performance
(Chapter 6 and 7)
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5. Organization of a Computer
Five classic components of a computer – input, output, memory, datapath, and control
datapath + control = processor (CPU)
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6. AMD’s Barcelona Multicore Chip
Four out-of- order cores on one chip
1.9 GHz clock rate
65nm technology
Three levels of caches (L1, L2, L3) on chip
Integrated Northbridge
Core 1
512KB L2
512KB L2
Core 2
2MB shared L3 Cache
Northbridge
Core 3
512KB L2
512KB L2
Core 4
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7. Computer Organization & Design by Patterson & Hennessy
Function Units in a Computer
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8. Computer Organization & Design by Patterson & Hennessy
Magnetic Storage
Source: Quantum Corp
Disk capacity increasing 60%/year for common form factor
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9. Classes of Computers
Desktop computers: Designed to deliver good performance to a single user at low cost usually executing 3rd party software, usually incorporating a graphics display, a keyboard, and a mouse
Servers: Used to run larger programs for multiple, simultaneous users typically accessed only via a network and that places a greater emphasis on dependability and (often) security
Supercomputers: A high performance, high cost class of servers with hundreds to thousands of processors, terabytes of memory and petabytes of storage that are used for high-end scientific and engineering applications
Embedded computers (processors): A computer inside another device used for running one predetermined application. Very often cost, power, and failure rate are more important than performance.
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10. (embedded growth >> desktop growth !!!)
Growth in Embedded Processor Sales
(embedded growth >> desktop growth !!!)
Cell phone sales exceeded PCs by only a factor of 1.4 in 1997, but the ratio grew to 4.5 in 2007.
The total number in use in 2004 estimated to be about 2.0B televisions, 1.8B cell phones, and 0.8B PCs. As the worlds population was about 6.4B in 2004, that makes about 1PC, 2.2 cell phones, and 2.5 televisions for every 8 people on the planet.
Where else are embedded processors found?
CS224 Spring 2012

11. Dual Core Itanium with 1.7B transistors
Moore’s Law
In 1965, Intel’s Gordon Moore predicted that the number of transistors that can be integrated on single chip would double about every two years
Dual Core Itanium with 1.7B transistors
feature size
&
die size
Courtesy, Intel ®

12. Computer Organization & Design by Patterson & Hennessy
Moore’s Law for CPUs and DRAMs
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13. Technology Scaling Road Map
Year
2004
2006
2008
2010
2012
Feature size (nm) 90 65 45 32 22
Intg. Capacity (BT) 2 4 6 16
Fun facts about 22nm transistors
120 million can fit on the head of a pin
You could fit more than 4,000 across the width of a human hair
If car prices had fallen at the same rate as the price of a single transistor has since 1968, a new car today would cost less than 1 cent
International Technology Roadmap for Semiconductors 13

14. Computer Organization & Design by Patterson & Hennessy
Semiconductors
50 year old industry
Still has continuous improvements, in each generation
New generation every 2-3 years
30% reduction in dimension  50% in area
30% reduction in delay  50% speed increase
Current generation: Reduce cost and increases performance
Processors are fabricated on ingots cut into wafers which are then etched to create transistors
Wafers are then diced to form chips, some of which have defects
Yield is the measurement of the good chips
Next generation: Larger with more functions
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15. Computer Organization & Design by Patterson & Hennessy
Main driver: device scaling ... .
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16. Semiconductor Manufacturing Process for Silicon ICs
After being sliced from the silicon ingot, blank wafers are put through 20 to 40 steps to create patterned wafers. These patterned wafers are then tested with a wafer tester, and a map of the good parts is made. Then, the wafers are diced into dies (see Figure 1.9). In this fi gure, one wafer produced 20 dies, of which 17 passed testing. (X means the die is bad.) The yield of good dies in this case was 17/20, or 85%. These good dies are then bonded into packages and tested one more time before shipping the packaged parts to customers. One bad packaged part was found in this final test
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17. What Happened to Clock Rates?
Clock rates hit a “power wall”
Packaging issues for laptop and desktop PC set the “power” limit at 100 Watts.

18. Processor performance growth flattens!
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19. The Latest Revolution: Multicores
The power challenge has forced a change in the design of microprocessors
Since 2002 the rate of improvement in the response time of programs on desktop computers has slowed from a factor of 1.5 per year to less than a factor of 1.2 per year
Since 2006, all desktop and server companies are shipping microprocessors with multiple processors – cores – per chip
Product
AMD Barcelona
Intel Nehalem
IBM Power 6
Sun Niagara 2
Cores per chip 4 2 8
Clock rate
2.5 GHz
~2.5 GHz?
4.7 GHz
1.4 GHz
Power
120 W
~100 W?
94 W
Multicore issues
Hard for programmers to write explicitly parallel programs - task scheduling with load balancing and minimal communication and synchronization overhead.
The plan is to double the number of cores per chip per generation (about every two years)
CS224 Spring 2012

20. Power as a Performance Metric
Power consumption – especially in the embedded market where battery life is important
For power-limited applications, the most important metric is energy efficiency
The book has an example on page 50 of the new SPECpower_ssj2008 benchmark and how it is calculated.

21. Computer Organization & Design by Patterson & Hennessy
Computer Architecture
Application
Operating
System
Compiler
Firmware
Instruction Set Architecture
Instr. Set Proc.
I/O system
Computer
Architecture
Logic Design
Implementation
Circuit Design
Layout
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22. Computer Organization & Design by Patterson & Hennessy
The Instruction Set: a Critical Interface
instruction set
software
hardware
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23. Computer Organization & Design by Patterson & Hennessy
Instruction Set Architecture
A very important abstraction
interface between hardware and low-level software
standardizes instructions, machine language bit patterns, etc.
advantage: different implementations (cost, performance, power) of the same architecture
disadvantage: sometimes prevents using new innovations
Common instruction set architectures:
IA-32, PowerPC, MIPS, SPARC, ARM, and others
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24. Computer Organization & Design by Patterson & Hennessy
Instruction Set Architecture
ISA, or simply architecture – the abstract interface between the hardware and the lowest level software that encompasses all the information necessary to write a machine language program, including instructions, registers, memory access, I/O, …
ISA Includes
Organization of storage
Data types
Encoding and representing instructions
Instruction Set (or opcodes)
Modes of addressing data items/instructions
Program visible exception handling
Specifies requirements for binary compatibility across implementations (ABI)
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25. Computer Organization & Design by Patterson & Hennessy
Case Study: MIPS ISA
Instruction Categories
Load/Store
Computational
Jump and Branch
Floating Point
Memory Management
Special
R0 - R31 PC HI LO
3 Instruction Formats, 32 bits wide OP rs rt rd sa
funct OP rs rt
immediate OP
jump target
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26. Computer Organization & Design by Patterson & Hennessy
Execution Cycle
Instruction
Fetch
Obtain instruction from program storage
Instruction
Decode
Determine required actions and instruction size
Operand
Fetch
Locate and obtain operand data
Compute result value or status
Execute
Result
Store
Deposit results in storage for later use
Next
Instruction
Determine successor instruction
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27. Computer Organization & Design by Patterson & Hennessy
Levels of Representation
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
High Level Language Program
Compiler
lw $15, 0($2)
lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
Assembly Language Program
Assembler
Machine Language Program
Machine Interpretation
Control Signal Specification
ALUOP[0:3] <= InstReg[9:11] & MASK
[i.e.high/low on control lines]
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28. Advantages of HLLs Higher-level languages (HLLs)
Allow the programmer to think in a more natural language and for their intended use (Fortran for scientific computation, Cobol for business programming, Lisp for symbol manipulation, Java for web programming, …)
Improve programmer productivity – more understandable code that is easier to debug and validate
Improve program maintainability
Allow programs to be independent of the computer on which they are developed (compilers and assemblers can translate high-level language programs to the binary instructions of any machine)
Emergence of optimizing compilers that produce very efficient assembly code optimized for the target machine
Higher-level languages (HLLs)
Compilers convert source code to object code
Libraries simplify common tasks
For lecture
CS224 Spring 2012