1. EEE1012 Introduction to Electrical & Electronics Engineering Chapter 7: Field Effect Transistor by Muhazam Mustapha, October 2010

2. Learning Outcome Be able to explain some basic physical theory and operation of FET Be able to do calculation on DC and AC analysis on FET circuit By the end of this chapter students are expected to:

3. Chapter Content Theory of FET FET Operation DC Analysis AC Analysis

4. Field Effect Transistor

5. FET is a piece of electronic device that conducts electricity by the control of a gate It can be considered as a voltage controlled resistor or voltage controlled current source Gate Current flows through the center body of channel from terminals called drain to source Gate is a plate not touching the substrate Drain Source Channel

6. FET Types There are many types of FET –MOSFET – Metal Oxide Semiconductor FET –JFET – Junction FET –NMOS – n-channel MOSFET –PMOS – p-channel MOSFET We will cover mostly NMOS

7. Channel Types FET is also characterized by its channel n-channel –The majority carrier in the channel is electron p-channel –The majority carrier in the channel is hole

8. Modes Enhancement mode –FET is normally NOT conducting current even when given voltage at drain and source –Gate is to increase the current Depletion mode –FET is normally conducting current when given voltage at drain and source –Gate is to decrease the current

9. Depletion Mode Drain Source Gate p-channel –Current flow is reduced by putting a positive voltage at gate to repel holes flow and finally block the current –The more positive the gate, the less current flow +ve −ve p-channel Hole Flow Gate’s electric field repelling holes +ve

10. Depletion Mode Drain Source Gate n-channel –Current flow is reduced by putting a negative voltage at gate to repel electrons flow and finally block the current –The more negative the gate, the less current flow +ve −ve n-channel Electron Flow Gate’s electric field repelling electrons −ve

11. Enhancement Mode (PMOS) Drain Source Gate p-channel –When negative voltage is put to drain that is made of highly p dopant (p + ), reverse bias junction is formed at drain – hence no current flows –Negative voltage is put to gate to attract holes and effectively compensate the reverse biases – until current can flow −ve +ve n-substrate Gate’s electric field attracting holes p-channel formation p+p+ −ve p+p+ Hole Flow

12. Enhancement Mode (NMOS) Drain Source Gate n-channel –When positive voltage is put to drain that is made of highly n dopant (n + ), reverse bias junction is formed at drain – hence no current flows –Positive voltage is put to gate to attract electrons and effectively compensate the reverse biases – until current can flow +ve −ve p-substrate Gate’s electric field attracting electrons n-channel formation n+n+ +ve n+n+ Electron Flow

13. Circuit Symbol and Notations n-channel p-channel DepletionEnhancementJFET

14. Operation Region

15. I-V Characteristic Ohmic Region V GS = 5.0V V GS = 4.5V V GS = 4.0V V GS = 3.5V V GS = 3.0V V GS = 2.5V I D, mA Saturation Region Cutoff Region V DS, V 0 1 2 3 4 5 6 7 8 9 15 10 5 0

16. Operation Region Cutoff –V GS < V T and V GD < V T –No current flow Ohmic / Triode –V GS > V T and V GD > V T –Linear I-V characteristic

17. Operation Region Saturation –V GS > V T and V GD < V T –I D is controlled by V GS (Saturation Region Formula): Conductance parameter Threshold voltage – minimum voltage to form a conducting channel

18. FET In Digital Circuit

19. NAND, NOR and NOT Gates

20. DC Biasing

21. FET Biasing Biasing an FET means putting its V DS and I D into a desired position in the I D -V DS graph This is done normally if we want the FET to operate in saturation region The biasing process is a little tricky since I D is controlled by V G – not directly by V DS Refer to Giorgio Rizzoni’s Fundamentals of Electrical Engineering: Chapter 11.3, Example 11.4

22. FET Biasing The biasing formula will also be a little different from BJT since in FET saturation region we have formula: I D = K(V GS -V T ) 2 Another difference is that I G is zero (whereas I B is not zero in BJT) since the gate is not in contact with the channel Refer to Giorgio Rizzoni’s Fundamentals of Electrical Engineering: Chapter 11.3, Example 11.4

23. FET Biasing The position of the biased FET’s V DS and I D is called Q point The value of V GS is also required for the biasing There are a few biasing configuration exist, but for the purpose of non-EE class, we will only study the most popular configuration called self- bias common source configuration –Refer to Giorgio Rizzoni’s Fundamentals of Electrical Engineering Figure 11.8(a) Refer to Giorgio Rizzoni’s Fundamentals of Electrical Engineering: Chapter 11.3, Example 11.4

24. FET Biasing R2R2 R1R1 V DD RDRD RSRS IGIG IDID V DS + − V GS + − Refer to Giorgio Rizzoni’s Fundamentals of Electrical Engineering: Chapter 11.3, Example 11.4 RGRG RDRD RSRS IGIG IDID V DS + − V GS + − V GG Thevenin’s Equivalent V GG = (V DD )(R 2 )/(R 1 +R 2 ) R G = R 1 || R 2 V DD

25. FET Biasing The target of biasing process is to find the value of the resistors so that Q point is position at around V DD /2 in the I D -V DS characteristic graph R 1 and R 2 will determine V GS V GS will determine I D I D = K(V GS −V T ) 2 Then from KVL, V DS = V DD −I D (R D +R S ) –This equation is what called load-line equation Refer to Giorgio Rizzoni’s Fundamentals of Electrical Engineering: Chapter 11.3, Example 11.4

26. FET Biasing Steps: R 1 and R 2 will be combined using Thevenin’s theorem to form R G Use KVL on GS loop to get V GS from R S and I D Use saturation region formula to get a quadratic equation on V GS or I D, then solve the other one Use KVL on DS loop (load-line equation) with the required V DS for the Q point to get R D Refer to Giorgio Rizzoni’s Fundamentals of Electrical Engineering: Chapter 11.3, Example 11.4

27. FET Biasing Class discussion: Giorgio Rizzoni’s Fundamentals of Electrical Engineering: pages 500 – 501, Example 11.4

28. AC Analysis

29. AC analysis is done to determine the performance of FET amplifier circuit There are a few parameters of interest, like input and output resistance, but for the purpose of non-EE class, we will do only voltage gain (no current gain, why?) AC analysis is done after biasing is completed and assuming there is some AC signal being introduced into the circuit as superimpose on top of the DC values (biasing)

30. AC Analysis The oscillation of the input and output signals will be denoted by Δ (delta) For this class we will consider the I-V characteristic of the sinusoidal input and output signals will be the same as the DC relationship –next slide

31. AC Analysis R2R2 R1R1 V DD RDRD RSRS ΔVGΔVG ΔVOΔVO

32. AC Analysis Voltage Gain

33. AC Analysis In the formula for ΔV O, it only depends on ΔI D even though from the KVL at the output it should also depends on ΔI S. The reason for this is in real circuit we put a capacitor across R S which effectively SHORTS circuit R S when AC current flows – means we can disregard R S in AC analysis formula. R2R2 R1R1 V DD RDRD RSRS ΔVGΔVG ΔVOΔVO

34. AC Analysis Self exercise: Based on Giorgio Rizzoni’s Fundamentals of Electrical Engineering Example 11.4, get the V p-p of output if the V p-p of input is 5mV