1. Design of the Front-end Electronics for the GOSSIPO chip. Vladimir Gromov Electronics Technology NIKHEF, Amsterdam, the Netherlands CERN, July the 22 th, 2005

2. Highlights. Main functionalities of the GOSSIPO. Main objectives and principal block diagram of the prototype of the chip. Evaluation of the parasitic capacitances at the input of the charge-sensitive preamplifier. Injection of the input test signal. Design and performance of the charge-sensitive preamplifier. Design and performance of the current comparator and output LVDS driver. Design and performance of the bias circuit. Conclusion and plans.

3. The GOSSIPO chip. ( Gas On Slimmed Silicon Pixel) Cluster3 Cathode (drift) plane Micromegas Cluster2 Cluster1 Silicon wafer with read-out electronics on it Input pixel 1mm, 400Volts 50um, 400Volts 20um electron component, Qe=10% ion component, Qi =90% 0 10 20 30 time,ns Input current, nA Shape of the current signal coming on the pixel pad The Input signal. Signal, electrons THR=350e Gain=8000 Gain=4000 Gain=2000 Time-walk curve Time-walk vs pulse height distribution

4. Main features of the GOSSIPO chip. 1.There will no silicon sensor on the chip due to a novel concept of the particle detection that allows to circumvent major constrains related to that. 2.Low input parasitic capacitance and no need for the detector leakage current compensation at the input are the reasons to expect an outstanding performance of the design. Objectives for the prototype. Testing of the performance and the functionality of the Front-end electronics on the bare chip (without InGrid and with InGrid on it). The design is expected to demonstrate: a) low-threshold operation (THR=350e). b) fast pulse response (δ-response peaking time ≈ 36ns, real signal response peaking time ≈ 52ns ). c) low analog power dissipation (≈ 1.7uW/channel for 1.2V supply). d) low channel-to-channel threshold dispersion (σ THR ≈140e). e) low parasitic feedback cross-talk.

5. Principal block diagram of the GOSSIPO front-end circuit. C fb ≈ 1fF R fb ≈ 80MΩ C par ≈ 30fF I det (t) C c ≈ 200fF V ref I thr =42nA R l ≈ 1kΩ Charge sensitive preamplifier Current Comparator with DC hysteresis LVDS driver Bias generator Channel#1 Channel#2 Channel#3 Channel#4 C fb ≈ 1fF R fb ≈ 80MΩ C par ≈ 30fF I det (t) Charge sensitive preamplifier Voltage follower Outputs Channel#5 Bias control R on ≈ 2GΩ Voltage-to-current converter

6. Parasitic capacitances associated with the input pad. noise peaking time charge collection Micromegas Input pad Substrate of the wafer C p-grid C p-sub C p-p C par = C p-grid + C p-p + C p-sub, where C p-sub is pad-to-substrate capacitance coupling C p-grid is pad-to-Micromegas capacitance coupling C p-p is pad-to-pad capacitance coupling.

7. Evaluation of the pad-to-Micromegas parasitic capacitances C p-grid. C=1.8fF when R=25um, d=50um R - is a radius of the pad. The pad is a circle. d - is pad-to-Micromegas distance.  0 - is vacuum dielectric constant. D Ideal boundless plane Ideal uniformly charged disk R Model for analytical calculations of the pad-to-Micromegas parasitic capacitance.

8. Evaluation of the pad-to-substrate parasitic capacitances C p-sub in 0.13um CMOS technology. ≈ 6um Substrate RInput pad (LM, copper 0.55um) MQ, copper 0.55um M6, copper 0.32um M5, copper 0.32um M4, copper 0.32um M3, copper 0.32um M2, copper 0.32um M1, copper 0.29um PC Via 2x2, 0.8um x 0.8um 0 5 10 15 20 25 R, um Extraction done by DIVA with CDS_coeffgen_Cap option Extraction done by DIVA with Raphael_Cap option Analytical calculation C p-sub =27fF R=25um, Layout of the input pad coupling in 0.13um CMOS technology (CMOS8SF, flavour LM 6_2). 30 25 20 C p-sub 15 fF 10 5 0 Capacitive parasitics based on the physical design of the layout have been extracted within DIVA Extract rules supplied in the Design Kit. Both available methodologies (CDS_coeffgen_Cap and Raphael_Cap) have been used. Suggested Diva Deck Extraction Methodology (from the PDK User’s guide) - generate a trial test structure which mimic possible design geometries as much as possible. - run extraction tool for both methodologies. - review the capacitance numbers and use the tool that gives the more pessimistic results. Compare the numbers to hand calculations or a 3D field solver.

9. Evaluation of the pad-to-pad parasitic capacitances C p-p in 0.13um CMOS technology. Model for analytical calculations of the pad-to-pad parasitic capacitance. a b b Input pad C p-p Input pad c=0.55um where b is dimension of the pad, c is thickness of the pad, a is pad-to-pad distance, ε0 is vacuum dielectric constant, εr is relative permittivity of the medium Pad-to-pad layout 0 5 10 15 20 a,um Analytical calculation on the basis of the model. Extraction done by DIVA with Raphael_Cap option Extraction done by DIVA with CDS_coeffgen_Cap option Evaluation of the input pad-to-pad capacitances in 0.13um CMOS technology (CMOS8SF, flavour LM 6_2). Large pads (b=30um) 2.5 2 C p-p 1.5 fF 1 0.5 0

10. Injection of the input test signal. C par * = C par + C in, therefore C in << C par = 30fF C fb ≈ 1fF R fb ≈ 80MΩ C par ≈ 30fF U pulse (t) Charge sensitive preamplifier R t =50Ω C in ≈ 3fF U in ≈ 20mV Q in =C in U in ≈ 0.06fC (350e) Vertical Parallel Plate (VPP) capacitor in LM layer. C fringe =3.2fF Active pad d=550um a=1800nm 40um Test input !!! Accuracy of the fringe capacitors. Δa=50nm, Δa/a=3% (lithography accuracy) ± 25% Δd=±140nm, Δd/d=± 25% (LM layer thickness accuracy) Passive pad

11. The charge-sensitive preamplifier. The feedback capacitance. 1. Charge sensitivity: U amplitude ≈ Q det / C fb 2. Charge collection (input impedance) C in * = A C fb ≈ 140fF C in * >> C par ≈ 30fF C fb ≈ 1fF R fb ≈ 80MΩ C par ≈ 30fF I det (t) Q det U(t) A≈140 Coaxial-like layout of the input interconnection. Extraction with the parasitics. Input pad Substrate C fb = 1fF C ** = 0.5fF C p-sub = 23fF 40um 0.18um 0.2um C ** ≈ 0.5fF !!! Accuracy of the fringe capacitor is ± 25% (metal layers accuracy)

12. The charge-sensitive preamplifier. The feedback resistor. C fb ≈ 1fF R fb ≈ 80MΩ C par ≈ 30fF I det (t) Δt det ≈ 30ns Q det U(t) A≈140 1.To avoid ballistic deficit: R fb C fb > Δt det =30ns R fb > 30MΩ C fb 2I p Output Silicon sensor C int IpIp I leak + I p I leak Classic F.Krummenacher charge sensitive preamplifier realizes large R fb and compensates for the detector leakage current. !!! C int → ∞ in order to avoid differentiation of the input signal. C fb Output Input There is no need to compensate for the detector leakage in GOSSIPO chip. !!! C int is not needed in this preamplifier and I p =I b. R fb ≈ 1/gm M1 +1/gm M2 ≈ 80MΩ,where gm is common-source transconductance of transistor. M1 M2 I b =1nA I p =I b =1nA

13. The charge-sensitive preamplifier. Channel-to-channel variation of the DC offset at the output. C fb =1fF K=127 V bias1 V bias2 I bias2 =2nA Vdd=1.2V Output Input I bias4 =1uA I bias3 =0.2uA M1 M2 M3 M5 M7 M6 M4 OPAMP A (jw) V bias3 I bias3 =1nA M8 M9 M10 Uout DC varies from channel to channel. Three source of mismatch are in the design: 1. Mismatch in the diffrential pair M1 vs M2 σ(δVg)=√2[(σ T M1 ) 2 +(σ β M1 Id M1 /gm M1 ) 2 ] ≈ √2σ T M1 2.Mismatch in the current mirrors M10 vs M8,M9 σ{[Id M8+ Id M9 - Id M10 ]- /[Id M8+ Id M9 ]}=[(σ β M10 ) 2 +(σ T M10 gm M10 /Id M10 ) 2 ] ≈ σ T M10 gm M10 /Id M10 3. Mismatch in the current mirrors M5 vs M4 σ(δId M5 /Id M5 )=√ 2[(σ β M5 ) 2 +(σ T M5 gm M5 /Id M5 ) 2 ] ≈ √ 2gm M5 /Id M5 σ T M5 Standard deviation of the statistical variations of Uout DC σ(δUout DC )=√ {(√2σ T M1 ) 2 + (2√2 σ T M5 gm M5 /gm M1 ) 2 + (σ T M10 gm M10 /gm M1 ) 2 } Monte-Carlo simulations in Cadence give σ(δUout DC ) = 20mV (170e). Ib=1nA

14. The charge-sensitive preamplifier. The OPAMP. C fb ≈ 1fF R fb ≈ 80MΩ C par ≈ 30fF I det (t) Q det U(t) OPAMP The OPAMP. A(jw)=gm T75 /[gds T75 (gds T73 /gm T73 )+gds T77 +jwC*] =140/(1+jw14ns) gm is common-source transconductance of transistor. gds is common-source output conductance of transistor C* is total parasitic capacitance at the output.

15. The charge-sensitive preamplifier. Real signal response and stability. Magnitude-to-frequency response Phase-to-frequency response Unity gain line Phase margin 62º Phase margin of the preamplifier. C fb ≈ 1fF R fb ≈ 80MΩ C par ≈ 30fF I det (t) Q det U(t) OPAMP Input signal 438e = 70aC Output signal Peaking time 44ns Amplitude 52mV 30ns Decay of the signal is proportional to exp(-t/80ns) Real signal response of the preamplifier.

16. The charge-sensitive preamplifier. Main specifications. Table1. R0um15um20um25um C par 0fF10fF20fF30fF Gain140mV/ke130mV/ke125 mV/ke120 mV/ke N sim 34e RMS43e RMS57e RMS71e RMS N cal 4.5e RMS21e RMS35e RMS46e RMS T p int 20ns27ns32ns36ns T p real 41ns46ns50ns52ns δU DC σ ≈ 170e P1.2uW/channel for 1.2V supply C fb ≈ 1fF R fb ≈ 80MΩ C par ≈ 30fF I det (t) Q det U(t) OPAMP Radius of the input pad Parasitic capacitance at the input of the preamplifier Charge sensitivity Input referred noise (Affirma SPECTRE simulation) Input referred noise (hand calculation of serial thermal noise ) Peaking time of the output signal when it is a δ-response. Peaking time of the output signal when it is the response to the real signal Power dissipation Channel-to-channel variation of the DC offset at the output.

17. Uout + Uout - -A Ithr Iin Uout + - Uout - Iin - Ithr T1 T2 Vt T2 =200mV ± 30nA !!! Ambiguity zone ± 30nA !!! Low Vt T1 =200mV High Low High Conversion to digital signal. Current comparator.(H.Traff 1992).

18. Design of the Current comparator as a current-to-voltage converter. Uout + Uout - Iin Vt=200mV gm=1.6u Vt=200mV gm=1.6u Vt=400mV T1 T2 T3 T4 Vbias Vt=200mV 33 130nA Gain open loop = gm T3 / gds T3 = 53 (High state) = 18 (Low state) Degradation of the output impedance of T3 in Low state causes drop of the open loop gain. U DC =300mV Zin Freg, 10MHz High state. Iin = 60nA 500kΩ 40kΩ 14kΩ Low state. Iin = - 60nA Ambiguity state. Iin = 0nA. Zin=1/ [ gm T1,T2 Gain open loop ]

19. Interface to the Current comparator. Design of the ac- coupled voltage-to-current converter. Charge sensitive Preamplifier is a Current-to-voltage converter Voltage-to-current converter Current Comparator is a current-to-voltage converter voltagecurrent M1M2 Vbias1 Vbias2 Vbias3 Iout Uin I bias1 =200nA Cc=200fF I thr =42nA 1. Differentiation time constant of the AC-coupling: Cc Ron = 200usec >> signal duration time. 2. Gain = Iout/Uin = 0.5 gm T1 = 90nA/52mV (438e). 3. Channel-to-channel Gain variation: σ(δGain/Gain) = 10% (44e). 4. Output impedance = 1/ gds T3 = 100 MΩ. 5. Channel-to-channel variation of the output DC current: σ(δIout DC ) = 24nA (120e). M3 LVDS Driver Ron=1G ΩM4

20. Design of the complete comparator with DC hysteresis. Vbias1 Vbias2 Vbias3 Iout Uin I thr =42nA Uout + Uout - Vbias 33 130nA U DC =300mV Charge sensitive Preamplifier is a Current-to-voltage converter Voltage-to-current converter Current Comparator is a current-to-voltage converter voltagecurrent LVDS Driver voltage I thr =15nA Hysteresis or positive feedback allows to avoid too short pulses and double pulses at the output of the comparator. U(THR up )-U(THR down ) = 15nA(73e) σ noise = 0.2 U(THR up ) = 75e THR up THR down ≈ σ noise

21. Design of the LVDS output driver. Charge sensitive Preamplifier is a Current-to-voltage converter Voltage-to-current converter Current Comparator is a current-to-voltage converter voltagecurrent LVDS Driver voltage I bias =21uA Rl=7kΩR2=7kΩ Uin + Uin - I bias =85uA R3=1kΩ R4=1kΩ Uout - Uout + ΔU= 100mV The Low Voltage Differential Driver (LVDS) delivers the digital signals to the external low impedance load. C par ≈ 8pF ΔU= 55mV C par ≈ 8pF

22. The signals in the design. Time-walk at the output of the LVDS driver as a function of the signal amplitude (Amp). Threshold = 350e. Input current signal coming from pixel pad Output of the preamplifier Output of the current comparator. Output of the LVDS driver. Threshold ΔT=45ns Amp=350e Amp=438e Amp=900e Amp=1800e Amp=9000e

23. Design of the bias circuit. Control determines current (voltage drop over R1). Cncap = 10fF (11fF/um 2 ) Ron=1GΩ W/L=0.16u/24u Vgs=38mW Vthr=250mV A filter is needed to suppress common bus noise. A 1 th order low-pass filter with cut-off frequency f cut-off = 1/[2π Ron Cncap] = 16kHz Vgs=38mW R1 Channel-to-channel spread of the output impedances T1…T4 is given as follows: σ(δ(g ds )/g ds )= σ(δVt) /[nΦ t ] ≈ 15% T1 T2 T3 T4

24. Conclusion and plans.. There will be no silicon sensor on the GOSSIPO chip due to a novel concept of the particle detection that allows to circumvent major constrains related to that.. Low input parasitic capacitance and no need for the detector leakage current compensation at the input are the reasons to expect an outstanding performance of the design.. Design of the GOSSIPO chip is in progress on the basis of the potentialities of the 0.13um CMOS. The following specification have been found feasible so far: a) parasitic input capacitance 10fF….30fF. b) input referred electronic noise σ noise = 70e (corresponds to THR=350e). c) δ-response peaking time ≈ 36ns, real signal response peaking time ≈ 52ns. d) analog power dissipation ≈ 1.7uW/channel for 1.2V supply (without LVDS driver). e) channel-to-channel threshold dispersion σ THR ≈140e.. There will be 4 individual channels on the chip. Each channel will be equipped with a charge- sensitive preamplifier ac-coupled to a current comparator with DC hysteresis and a LVDS driver.. Vertical Parallel Plate (VPP) or fringe capacitor seems to be suitable for injection of the test signal. The VPP-based capacitance is taken to implement the feedback capacitance in the preamplifier.. A dedicated circuit on the chip will provide all the channels with bias voltages (currents).. Low-pass filters have been added to each channel to avoid common bus noise.. We look to submit this prototype within CERN organized MPW run in December 2005.