1. Penn ESE370 Fall2013 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 28: November 15, 2013 Memory Periphery

2. Today Memory Periphery Sensing Driving Decode Penn ESE370 Fall2013 -- DeHon 2

3. Sensing Penn ESE370 Fall2013 -- DeHon 3

4. 4 SRAM Memory bit

5. Simulation W access =20 Penn ESE370 Fall2013 -- DeHon 5

6. Sense Small Swings What do we have to worry about? Penn ESE370 Fall2013 -- DeHon 6

7. Sense Small Swings Variation –Shift where inverter trip point is Systematic shifts that effect both lines –“Common mode” noise –E.g. Noise Voltage droop Penn ESE370 Fall2013 -- DeHon 7

8. Two Sense Amps 1.Clocked / Regenerative Feedback 2.Not clocked / Differential Sense Amp Goal: amplify small signal difference reject common mode noise Penn ESE370 Fall2013 -- DeHon 8

9. Differential Sense Amp Goal: –Reject common shift Penn ESE370 Fall2013 -- DeHon 9

10. Warmup What does this do? How do we size transistor? Penn ESE370 Fall2013 -- DeHon 10

11. Voltage Controlled Consider Vctrl as an analog input between 0 and Vdd-Vth What does this do? How does the voltage on V ctrl control operation? Penn ESE370 Fall2013 -- DeHon 11

12. DC Transfer Penn ESE370 Fall2013 -- DeHon 12

13. Idea Control Resistance to control trip point Set trip point based on second line Q: how set Vctrl? Penn ESE370 Fall2013 -- DeHon 13

14. Differential Sense Amp Penn ESE370 Fall2013 -- DeHon 14

15. What does this do? Output when: –In=Gnd? –In=Vdd? –Transfer curve? Penn ESE370 Fall2013 -- DeHon 15

16. “Inverter” Input high –Ratioed like grounded P Input low –Pulls itself up –Until V dd -V TP Penn ESE370 Fall2013 -- DeHon 16

17. DC Transfer Function Penn ESE370 Fall2013 -- DeHon 17

18. Differential Sense Amp Penn ESE370 Fall2013 -- DeHon 18

19. Diffamp Transfer Function in=/in, looks like “inverter” Deliberately low gain in mid region Ideal might be flat? Penn ESE370 Fall2013 -- DeHon 19

20. Differential Sense Amp “Inverter” output controls PMOS for second inverter Sets PMOS operating point –Voltage controlled resistance –Sets trip point Penn ESE370 Fall2013 -- DeHon 20

21. Differential Sense Amp What happens when o /in > in? o /in < in? Penn ESE370 Fall2013 -- DeHon 21

22. Differential Sense Amp View: –Current mirror –Biases where inverter operating Penn ESE370 Fall2013 -- DeHon 22

23. Differential Sense Amp View: – adjusting the pullup load resistance –Changing the trip point for “inverter” Penn ESE370 Fall2013 -- DeHon 23

24. DC Transfer /in with in=0.5V Penn ESE370 Fall2013 -- DeHon 24

25. DC Transfer Various in Penn ESE370 Fall2013 -- DeHon 25

26. DC Transfer Various in What is trip point when: In=0.3V? In=0.4V? In=0.5V? In=0.6V? In=0.7V? Penn ESE370 Fall2013 -- DeHon 26

27. After Inverter Penn ESE370 Fall2013 -- DeHon 27

28. Ramp 50mV Offset Penn ESE370 Fall2013 -- DeHon 28

29. Closeup 50mV Offset Penn ESE370 Fall2013 -- DeHon 29

30. Differential Sense Amp Does need to be sized There is a ratioed logic effect here Penn ESE370 Fall2013 -- DeHon 30

31. Regenerative Feedback Penn ESE370 Fall2013 -- DeHon 31

32. Connect to Column Equalize lines during precharge Penn ESE370 Fall2013 -- DeHon 32

33. Singled-Ended Read Penn ESE370 Fall2013 -- DeHon 33

34. 5T SRAM Penn ESE370 Fall2013 -- DeHon 34

35. Single Ended Given same problems –How sense small swing on single-ended case? Penn ESE370 Fall2013 -- DeHon 35

36. Single Ended Need reference to compare against Want to look just like bit line Equalize with bit line Penn ESE370 Fall2013 -- DeHon 36

37. Split Bit Line Split bit-line in half Precharge/equalize both Word in only one half –Only it switches Amplify difference Penn ESE370 Fall2013 -- DeHon 37

38. Open Bit Line Architecture For 1T DRAM Add dummy cells Charge dummy cells to V dd /2 “read” dummy in reference half Penn ESE370 Fall2013 -- DeHon 38

39. Memory Bank Penn ESE370 Fall2013 -- DeHon 39

40. Row Select Penn ESE370 Fall2013 -- DeHon 40

41. Memory Bank Penn ESE370 Fall2013 -- DeHon 41

42. Row Select Logically a big AND –May include an enable for timing in synchronous Penn ESE370 Fall2013 -- DeHon 42 How many transistors (per address bit)?

43. How tall is a row? Side length for cell of size: –1000 2 – 600 2 – 100 2 Penn ESE370 Fall2013 -- DeHon 43

44. 44 How tall is an AND? Penn ESE370 Fall2013 -- DeHon 2 6 6 3 2 2 44

45. Row Select How can we do better? –Area –Delay –Match to pitch of memory row Penn ESE370 Fall2013 -- DeHon 45

46. Row Select Compute inversions outside array –Just AND appropriate line (bit or /bit) Penn ESE370 Fall2013 -- DeHon 46

47. Row Select Share common terms Multi-level decode Penn ESE370 Fall2013 -- DeHon 47

48. Row Select Same number of lines Half as many AND inputs inside the row Penn ESE370 Fall2013 -- DeHon 48

49. Row Select: Precharge NAND Penn ESE370 Fall2013 -- DeHon 49

50. Row Select: Precharge NOR Penn ESE370 Fall2013 -- DeHon 50

51. Bus Drivers Penn ESE370 Fall2013 -- DeHon 51

52. Memory Bank Penn ESE370 Fall2013 -- DeHon 52

53. Tristate Driver Penn ESE370 Fall2013 -- DeHon 53

54. Tri-State Drivers Penn ESE370 Fall2013 -- DeHon 54

55. Idea Minimize area of repeated cell Compensate with periphery –Amplification (restoration) Match periphery pitch to cell row/column –Decode –Sensing –Writer Drivers Penn ESE370 Fall2013 -- DeHon 55

56. Admin Monday: in Detkin Lab –Read lab2 assignment before coming to class Tuesday: Proj2 Milestone due Wednesday: Lecture Penn ESE370 Fall2013 -- DeHon 56