1. EKT 121 / 4 DIGITAL ELECTRONICS I FIRST DAY SLIDES

2. Lecturers: –Pn. Norina bt. Idris Jejawi Blok A, Level 1 Jejawi Blok A, Level 1 04 – 9798387 04 – 9798387 012 – 4037775 012 – 4037775 –En. Muammar Jejawi Blok B, Level 2

3. PLV: –Pn. Wan Azlianawati –Pn. Norlida Makmal Elektronik, Kubang Gajah

4. Class Representatives

5. Class Lecture: –Friday, 9-10 am, DKP 3 –Monday, 11 am – 1 pm, DKP 1 Labs: –Micro-E: Tuesday, 8-10 am, MKG3 –Electronics: Wednesday, 1-3 pm, MKG1

6. What to expect & do … In Class To do: –Sign up the attendance sheet –Do not be NOisY.. –Pay attention To expect: –Surprise quizzes –In-class assignments

7. What to do after class … Read the textbook Assignment Folder –Answer the given questions –Hand in before semester break, and before study break

8. What to expect & do … In Lab To do: –Do your oWn work.. –Do not cOPy others… –Bring your own “test pen” and “IC extractor” –Submit the lab sheet To expect: –Lab Test

9. What to do after lab … Do the lab report (on your own!!) –Follow the template given on portal –Submit each __?__ day to the lab

10. Grading: –50% - Final exam –25% - Labs (Lab & Lab Test) –20% - Tests –5% - Tutorial/Assignment/Quizzes References: –Floyd, Digital Fundamentals, Prentice Hall. –Bignel & Donovan, Digital Electronics, Thomson Learning. –Tocci, Digital Systems – Principles & Applications, Prentice Hall.

11. Text Book: –Digital Electronics Design, Prentice Hall. –Will be available on 15 th January 2007. –Price = RM 60. –Will be used in Digit I & Digit II.

12. Teaching Plan

13. Chapter 1: Introduction Number & Codes Boolean Algebra Basic Logic Gates OUTLINE

14. Chapter 2: Combinational Logic Circuit Arithmetic Converter (Encoder & Decoder) MUX / DEMUX Parity Generator Checker OUTLINE

15. Chapter 3: Sequential Logic Flip-flop & Register Shift Register Counter State Diagram OUTLINE