1. REGISTER MANAGMENT TOOL Preformed by: Liat Honig Nitzan Carmel Supervisor: Moshe Porian Date: 12/11/2012 Duration: Two Semesters Final presentation – Part A

2. M ANY TEAMS NEED TO CREATE THEIR OWN REGISTER BLOCKS FOR FPGA SYSTEMS. L EADING TO BUGS Double Effort T HE S OLUTION A R EGISTER M ANAGEMENT T OOL Automatically generates registers according to a required specification using a smart interface!

3. I NSERT YOUR PROJECT ’ S SPECIFICATIONS TO THE GUI A UTOMATICALLY CREATE VHD AND HSID FOR REGISTER BLOCKS ! A UTO R EG – A SMART REGISTER MANAGEMENT TOOL

4. Project Goals o Determine and characterize a local bus for communication with all the register slave blocks. o Generic Implementation that allows reuse in multiple projects. o Encapsulation of implementation, which will be hidden from the user. T HE S OLUTION – A R EGISTER M ANAGEMENT T OOL Creates unity in the registers VHD files Automatically generates registers according to the required specification. Enables REUSE Saves money and resources

5. Project Goals o Determine and characterize a local bus for communication with all the register slave blocks. o Generic Implementation that allows reuse in multiple projects. o Encapsulation of implementation, which will be hidden from the user. T HE S OLUTION – A R EGISTER M ANAGEMENT T OOL Creates documentation for the components created Leads to an organized – HSID Alarms in case of incorrect input Manages the registers through the entire project

6. Project Goals o Determine and characterize a local bus for communication with all the register slave blocks. o Generic Implementation that allows reuse in multiple projects. o Encapsulation of implementation, which will be hidden from the user.

7. P ROJECT S PECIFICATIONS 1. Writing a GUI interface through which the user will determine a variety of attributes. 4. No special license will be needed to operate the tool, an EXE file will be given to the user. 3. VHDL: VHD files Local Bus Master Simulation Environment 2. Interactivity - The tool will provide feedback for user errors and will provide a summary output. 5. HSID will be generated under IEEE standards (IP-XACT)

8. P ROJECT S TEPS 1. Determine the implementation platform of the user interface and data processing: Excel/MATLAB/C++/C#/JAVA. 2. Full characterization of the tool capabilities. 3. Learning the working environment (Wishbone protocol, advanced VHDL coding, MODELSIM simulation environment). 4. VHDL generic design and simulation. 5. Implementing the GUI (Graphic User Interface) 6. Implementing Automatic VHDL generation. 7. Final MODELSIM and MATLAB Simulations.

9. VHDL I MPLEMENTATION

10. Project Goals o Determine and characterize a local bus for communication with all the register slave blocks. o Generic Implementation that allows reuse in multiple projects. o Encapsulation of implementation, which will be hidden from the user. G ENERAL D ESCRIPTION Block Local Bus Chip data I/O Register access Register Block

11. Project Goals o Determine and characterize a local bus for communication with all the register slave blocks. o Generic Implementation that allows reuse in multiple projects. o Encapsulation of implementation, which will be hidden from the user. VHDL T OP A RCHITECTURE Block_A_reg_top Function_2 Function_3 Function_1 Block A Reg_status_1 Wishbone Master Reg_enable_2 func_err_3 resetclk

12. o Determine and characterize a local bus for communication with all the register slave blocks. o Generic Implementation that allows reuse in multiple projects. o Encapsulation of implementation, which will be hidden from the user. WB Slave Reg1 Reg2 Reg3 Reg4 Priority Encoder reg_chosen 4 WB Master Functional Block Data from chosen register Inputs from block Outputs to block Block_A_reg_top R EG B LOCK A RCHITECTURE

13. W ISHBONE - OPEN SOURCE PROTOCOL Block C clk_i cyc_i stb_i adr_i dat_i dat_o ack_o Stall_o we_i Block B WB Master Block A

14. W ISHBONE S LAVE C OMPONENT Idle wr_en=‘0’ rd_en=‘0’ Idle wr_en=‘0’ rd_en=‘0’ Read Cycle rd_en=‘1’ Read Cycle rd_en=‘1’ (wbs_cyc_i ) ● (wbs_stb_i) Active Cycle wbs_stall_o=‘1’ Active Cycle wbs_stall_o=‘1’ Write Cycle wr_en=‘1’ Write Cycle wr_en=‘1’ wbs_we_i Cycle Finished wbs_ack_o=‘1’ Cycle Finished wbs_ack_o=‘1’ dout_valid din_ack wbs_cyc_i WB Slave gen_reg Functional Block

15. gen_reg Component Idle reg_chosen =‘0 din_ack=‘0’ dout_valid=‘0’ Idle reg_chosen =‘0 din_ack=‘0’ dout_valid=‘0’ Read action addr==reg addr The Register is chosen reg_chosen=‘1’ The Register is chosen reg_chosen=‘1’ Write action addr==reg addr rd_en wr_en addr==reg addr Invalid Read Action dout_valid=‘0’ Invalid Read Action dout_valid=‘0’ Valid Read Action dout_valid=‘1’ Valid Read Action dout_valid=‘1’ Valid Write Action din_ack=‘1’ Valid Write Action din_ack=‘1’ Invalid write Action din_ack=‘0’ Invalid write Action din_ack=‘0’ Register type is W Register type is R/RW/COR/CONST Register type is W/RWRegister type is R/COR/CONST WB Slave gen_reg Functional Block

16. G ENERIC I MPLEMENTATION

18. VHDL S IMULATION

19. S IMULATION E NVIRONMENT Macro Scripts

20. S IMULATION E NVIRONMENT Compilation Simulation Waveforms Test Bench Macro Scripts

21. S IMULATION E NVIRONMENT Macro Scripts Compilation Simulation Waveforms Test Bench Procedure called serially many times Comparison to expected values Reporting results to output file Waveforms Results Output File Simulation outputs Simulation input

22. T EST P LAN - O VERVIEW Testing small modules separately gen_reg.vhd: Read Write Read/Write Clear On Read Const. wbs_reg.vhd Read transactions (single/burst) Write transactions (single/burst) encoder_generic.vhd Then, testing the entire design Gen_block.vhd

23. T EST P LAN – C ASES Testing Regular Activity Various generic values for address width Various values for data Read/Write single/burst wishbone cycles for suitable registers Testing system boundaries Testing system generics

24. WB slave addr = 0010 COR addr = 1110 W/R Encoder reg_chosen 4 WB Master Functional Block........ “00000000” Write Request ‘00001101’ Write Request ‘00001101’ “00001101” E XAMPLES – W RITE AND R EAD REGISTER SIMULATION Legal addr. + Legal operation = Request granted! Legal addr. + Legal operation = Request granted!

25. WB slave addr = 0010 COR addr = 1110 W/R Encoder Reg_chose n 4 WB Master Functional Block........ Read request “00001101” E XAMPLES – W RITE AND R EAD REGISTER SIMULATION Legal addr. + Legal operation = Request granted! Legal addr. + Legal operation = Request granted!

26. WB slave addr = 0010 COR addr = 1110 W/R Encoder Reg_chose n 4 WB Master Functional Block........ Data from Register E XAMPLES – W RITE AND R EAD REGISTER SIMULATION

27. S CENARIO : WB MASTER WRITES 7 THEN 8 TO REGISTER din = 7 and then 8 wr_en = ‘1’ for 2 cycles E XAMPLES – W RITE AND R EAD REGISTER SIMULATION

28. dout = 7 and then 8 din_ack = ‘1’ for 2 cycles UPDATED DATA FROM WB MASTER IS TRANSFERRED TO REGISTER DIN _ ACK RISES, INDICATING DOUT IS UPDATED R EGISTER NOT INFLUENCED BY DATA FROM BLOCK ( REG _ IN _ B ) E XAMPLES – W RITE AND R EAD REGISTER SIMULATION R ESULTS – REQUEST IS LEGAL !

29. S CENARIO : WB MASTER TRIES TO READ FROM THIS REGISTER ’ S ADDRESS ( REGISTER ADDRESS IS 10) A LSO A LEGLAL REQUEST ! R ESULT : DOUT _ VALID RISES TO ‘1’ Dout_valid = ‘1’ rd_en = ‘1’ addr = 10 E XAMPLES – W RITE AND R EAD REGISTER SIMULATION

30. S CENARIO : WB MASTER TRIES TO READ FROM A DIFFERENT REGISTER ADDRESS N OT A LEGAL REQUST ! R ESULT : DOUT _ VALID IS ‘0’ INDICATING DATA IS NOT VALID FOR THE CURRENT CYCLE Dout_valid = ‘0’ rd_en = ‘1’ addr = 15 E XAMPLES – W RITE AND R EAD REGISTER SIMULATION

31. E XAMPLES - C LEAR O N R EAD REGISTER SIMULATION WB slave addr = 0010 COR addr = 1110 W/R Encoder Reg_chosen 4 Functional Block........ “00000000” WB Master Register written with ‘0’

32. WB slave addr = 0010 COR addr = 1110 W/R Encoder Reg_chosen 4 WB Master........ “00010000” E XAMPLES - C LEAR O N R EAD REGISTER SIMULATION Functional Block Register written with ‘1’

33. WB slave addr = 0010 COR addr = 1110 W/R Encoder Reg_chosen 4 Functional Block........ “00000000” “00010000” WB Master E XAMPLES - C LEAR O N R EAD REGISTER SIMULATION Register is not cleared until it is read Block clears input

34. WB slave addr = 0010 COR addr = 1110 W/R Encoder Reg_chosen 4 Functional Block........ “00000000” WB Master E XAMPLES - C LEAR O N R EAD REGISTER SIMULATION Register is cleared Register is read

35. G RAPHICAL U SER I NTERFACE

36. Easy to use user experience Feedback is provided in real time Data is filled automatically if possible Easy project view and management Data and Address can be represented in both Hexadecimal and Decimal formats R EQUIREMENTS FROM GUI

37. O PENING S CREEN – PROJECT SETTINGS Settings made for the entire project Choose a protocol Specify address width Choose address radix Specify data width Choose data radix Specify number of blocks Specify a directory to save the generated files Browser for finding the requested directory

38. O PENING S CREEN – PROJECT SETTINGS Settings made for the entire project Choose a protocol Specify address width Choose address radix Specify data width Choose data radix Specify number of blocks Specify a directory to save the generated files Continue to next screen

39. 2 ND S CREEN – E DIT B LOCK SETTINGS Settings made for the specific block Specify a name Provide a description (optional) Opens text editor

40. 2 ND S CREEN – E DIT B LOCK SETTINGS Settings made for the specific block Specify a name Provide a description (optional) Specify an initial address Specify number of registers choose reset polarity back to project settings delete current block Continue to next screen Navigation tree view

41. 3 RD SCREEN – E DIT REGISTER SETTINGS Settings made for a specific register Specify a name Provide a description Choose register type Specify the offset address Specify the initial data value Navigation tree view Back to block settings delete current register

42. 3 RD SCREEN – E DIT REGISTER SETTINGS Settings made for a specific register Specify a name Provide a description Choose register type Specify the offset address Specify the initial data value

43. T OP MENUS File menu Help menu Create a new project Open an existing project Save project as Save current project Close current project Exit AutoReg About AutoReg Open user guide Generate menu Generate VHDL files Report for errors

44. T REE V IEW “ Top View ” of the entire project Automatically sorted by the absolute address Allows easy navigation between all the screens and components Addresses and names are filled automatically Navigation is blocked when errors or missing data is found in the current window

45. T REE V IEW Easy to use user experience Data is filled automatically if possible Easy project view and management

46. E RRORS D ISPLAY AutoReg notifies the user and prevents access to some contents in the project whenever: Data isn’t legal/valid/ complete Addresses/bits are overlapping Before Deleting an object 2. Addresses and data must be positive numbers within the user-determined range 1. Names must be valid VHDL names 3. Some necessary inputs is missing or invalid data was inserted

47. E RRORS D ISPLAY AutoReg notifies the user and prevents access to some contents in the project whenever: Data isn’t legal/valid/ complete Addresses/bits are overlapping Before Deleting an object 2. Bits defined under “Special bits” must not overlap 1. Addresses/ names must not overlap

48. E RRORS D ISPLAY AutoReg notifies the user and prevents access to some contents in the project whenever: Data isn’t legal/valid/ complete Addresses/bits are overlapping Before Deleting an object 2. User is prompt “Are you sure?” before deleting a block or a register 1. User is prompt to save changes before exiting the project

49. E RRORS D ISPLAY AutoReg notifies the user and prevents access to some contents in the project whenever: Data isn’t legal/valid/ complete Addresses/bits are overlapping Before Deleting an object In part B of the project – a conclusive report before generating the VHDL code Easy to use user experience Feedback is provided in real time

50. C ONCLUSIONS

51.  VHDL: Problem: during the simulation ( of a read cycle) we saw an unexpected glitch. Observation: the simulator works in series (and not in parallel). This caused unexpected behavior and the glitch to appear. Solution: using a macro file instead of a TB for this simulation showed there wasn’t a glitch at all! D EBUG, SOLUTIONS AND CONCLUSIONS

52.  GUI: Problem: as the GUI developed, we had to duplicate a lot of code for the different screens and functions of the GUI, resulting in a “pumped” code. Solution:  Moving some of the duplicated code into side-functions that made the code more readable and easy to maintain.  Later in the project we used more side functions in advance which proved to be a good decision. D EBUG, SOLUTIONS AND CONCLUSIONS

53.  GUI: Problem: The requirements from the GUI changed frequently through the work, causing many code re-writes and need to perform wide changes to the program and patch-like code. Conclusion: Plan the details in advance.

54. P LAN FOR P ART B 1.Creating a conclusive report that will show up at the end of the GUI. 2.Programing the Generation of VHDL files out of the GUI inputs 3.Creating an HSID for the registers with IP-XACT format XML. 4.Performing initial synthesis.

55. S CHEDULE FOR PART B Due DateTask 20.11.12Creating a conclusive report 1.1.13Creating an HSID with IP- XACT format XML 1.2.13Generation of VHDL 1.2.13-1.3.13Exams 15.3.13Initial synthesis 15.4.13Project Document and Final Presentation

56. DEMO http://www.youtube.com/watch?v=U3GVYfzikqM

57. S UGGESTIONS FOR A LATER PROJECT 1.An option to create a wide register (more than one address). 2.Support other protocols (not wishbone only) 3.Support more register types 4.Add a possibility to mix between the bits of the same register when it comes to access manners. 5.Support boards and not just on FPGA 6.Search and filter possibilities 7.Copy-Paste possibilities

58. S UGGESTIONS FOR A LATER PROJECT 8. Creating a database with options to import and export 9. An option to duplicate, add or delete a register using a right-click option from the tree view. 10. Unifying the edit_block figure and the edit_reg figure to prevent window from “jumping” 11. Under the help menu, add a keyboard map for all keyboard shortcuts of the GUI.

59. T HE E ND