1. Automating Shift-Register-LUT Based Run-Time Reconfiguration Karel Heyse, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt Karel.Heyse@UGent.be

2. Run-Time Reconfiguration (RTR) Changing (part of) circuit at run-time To save area, power, time … money ARC 20122 z z z z z z z z z z z z i 0-3 f(i 0-3 )g(i 0-3 ) h(i 0-3 )

3. Run-Time Reconfiguration – cont. Reconfiguration time – Time during which (part of) circuit is disabled – Can nullify gains of RTR Defines when RTR is feasible – Faster reconfiguration is important ARC 20123 SRL reconfiguration

4. SRL Reconfiguration methods ICAP How: Similar to configuration interface, frame based SRL reconfiguration How: Shift-register functionality of LUT’s truth table ARC 20124 inputsshift-in shift-enable shift-clock shift-out output SRL

5. Reconfiguration methods – cont. SRL reconfiguration + Very fine grained + Lower overhead + Bandwidth adjustable  FAST − Only LUTs TLUTMAP ARC 20125 ICAP − Coarse grained − Higher overhead − Fixed bandwidth + Full reconfiguration

6. TLUTMAP - Technology mapper Takes an HDL design with some slow inputs Creates configuration: – Dynamically specialisable for the slow inputs – By reconfiguring only part of the LUTs Smaller & faster specialised design – FIR filter: -39% LUTs, +38% max clock freq. – TCAM: -66% LUTs, +30% max clock freq. Fast RTR ARC 20126

7. You are here ( ★ ) Run-time reconfiguration Reconfiguration methods TLUTMAP – Technology mapper Generating reconfiguration chains Modelling as mTSP Solution method Results ARC 20127

8. Generating reconfiguration chains SRLs have to be chained, connected to configuration manager ARC 20128 Configuration manager

9. Optimising reconfiguration chains Influence on the design – Shares routing resources: routability, clock speed Minimise combined length of reconfiguration chains Influence on the reconfiguration time – Clock cycles Minimise #SRLs in longest chain – Clock speed reconfiguration Minimise longest connection ARC 20129

10. Modelling as mTSP We chose: Generating chains after placement – Position of SRLs fixed & known Model: multiple Travelling Salesman Problem – Minimise influence on design ARC 201210

11. Constrained mTSP Extra constraints to optimise reconfiguration time – Minimise # cities per salesman – Minimise longest link ARC 201211

12. Solution method: Simulated Annealing Summary – Iterative heuristic: Repetitive small, random alterations to a solution – Temperature ( T ): Starts high: exploration Ends low: converge to minimum ARC 201212

13. Solution method: Simulated Annealing – cont. Solution space – Common starting point for salesmen – No fixed end point for salesmen – Every salesman visits same number of cities (±1) Minimise # cities per salesman ARC 201213

14. Solution method: Simulated Annealing – cont. Random alterations ARC 201214 1) 2)

15. Solution method: Simulated Annealing – cont. Cost function ARC 201215

16. Experimental results Designs – TCAM: 60% reconfigurable LUTs – FIR filter: 37% reconfigurable LUTs Evaluated using Xilinx Tools – Flow: Place Insert reconfiguration chains Place & route ARC 201216

17. Results: Clock of the design ARC 201217 Relative to design without reconfiguration chains Averaged over experiments with 1, 4, 16 and 32 chains

18. Results Second placement step – VPR: -4% to -28% clock speed – Xilinx: +130% longer reconfiguration chain Number of reconfiguration chains – No influence on clock design – Small influence on clock reconfiguration Max clock speed reconfiguration – 1x to 2x clock speed design ARC 201218

19. Conclusion Automated method to generate reconfiguration chains Takes into account routability of design and reconfiguration speed Better than random, almost as good as manual Could be improved by avoiding second placement step ARC 201219

20. Automating Shift-Register-LUT Based Run-Time Reconfiguration Karel Heyse, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt Karel.Heyse@UGent.be