1. 1 VLSI Fabrication Technology

2. Microelectronic Circuits - Fifth Edition Sedra/Smith2 Copyright  2004 by Oxford University Press, Inc. Figure A.1 Silicon ingot and wafer slices.

3. Microelectronic Circuits - Fifth Edition Sedra/Smith3 Copyright  2004 by Oxford University Press, Inc. Figure A.2 (a) An 8-pin plastic dual-in-line IC package, (b) A 16-pin surface mount package.

4. Microelectronic Circuits - Fifth Edition Sedra/Smith4 Copyright  2004 by Oxford University Press, Inc. Figure A.3 A typical n-well CMOS process flow. (a) Define n-well diffusion (mask #1) (b) Define active regions (mask #2) (e) n+ diffusion (mask #4) (f) p+ diffusion (mask #5) (c) LOCOS oxidation (g) Contact holes (mask #6)

5. Microelectronic Circuits - Fifth Edition Sedra/Smith5 Copyright  2004 by Oxford University Press, Inc. Figure A.3 (Continued) (d) Polysilicon gate (mask #3) (h) Metallization (mask #7)

6. Microelectronic Circuits - Fifth Edition Sedra/Smith6 Copyright  2004 by Oxford University Press, Inc. Figure A.4 Cross-sectional diagram of an n- and p-MOSFET.

7. Microelectronic Circuits - Fifth Edition Sedra/Smith7 Copyright  2004 by Oxford University Press, Inc. Figure A.5 Cross sections of resistors of various types available from a typical n-well CMOS process.

8. Microelectronic Circuits - Fifth Edition Sedra/Smith8 Copyright  2004 by Oxford University Press, Inc. Figure A.6 Interpoly and MOS capacitors in an n-well CMOS process.

9. Microelectronic Circuits - Fifth Edition Sedra/Smith9 Copyright  2004 by Oxford University Press, Inc. Figure A.7 A pn junction diode in an n-well CMOS process.

10. Microelectronic Circuits - Fifth Edition Sedra/Smith10 Copyright  2004 by Oxford University Press, Inc. Figure A.8 Cross-sectional diagram of a BiCMOS process.

11. Microelectronic Circuits - Fifth Edition Sedra/Smith11 Copyright  2004 by Oxford University Press, Inc. Figure A.9 A lateral pnp transistor.

12. Microelectronic Circuits - Fifth Edition Sedra/Smith12 Copyright  2004 by Oxford University Press, Inc. Figure A.10 p-Base and pinched p-base resistors.

13. Microelectronic Circuits - Fifth Edition Sedra/Smith13 Copyright  2004 by Oxford University Press, Inc. Figure A.11 Cross-sectional diagram of a symmetrical self-aligned npn SiGe heterojunction bipolar transistor (HBT).

14. Microelectronic Circuits - Fifth Edition Sedra/Smith14 Copyright  2004 by Oxford University Press, Inc. Figure A.12 A CMOS inverter schematic and its layout.

15. Microelectronic Circuits - Fifth Edition Sedra/Smith15 Copyright  2004 by Oxford University Press, Inc. Figure A.13 Cross section along the plane AA of a CMOS inverter.

16. Microelectronic Circuits - Fifth Edition Sedra/Smith16 Copyright  2004 by Oxford University Press, Inc. Figure A.14 A set of photomasks for the n-well CMOS inverter. Note that each layer requires a separate plate: (a), (d), (e), and (f) dark-field masks; (b), (c), and (g) clear-field masks.