1. U niversity of S cience and T echnology of C hina Design for Distributed Scheme of WCDA Readout Electronics CAO Zhe University of Science and Technology of China Feb 18, 2011 12011/02/18

2. U niversity of S cience and T echnology of C hina Outline Architectural of distributed scheme Detail describe of principle Prototype modules for verification Electronics for prototype detector 22011/02/18

3. U niversity of S cience and T echnology of C hina Distributed Scheme for LHAASO 1 FEE for 9 PMTs 100 FEEs in 1 array 32011/02/18

4. U niversity of S cience and T echnology of C hina Architecture: Distributed vs. Lumped Digitalization on the frontend boards Only digital signals are required to transmitted over the long distance Ethernet, flat cable, or optical fiber can do the work The clock distribution will be critical in this architecture All the digitalization must be carried with the common precise clock Trigger decision will be another issue 42011/02/18

5. U niversity of S cience and T echnology of C hina Architectural of the distributed scheme Off-shore part FEE PMT readout Hits collection On-shore part Trigger: trigger form and distribution Clock: Common clock distribution Data processing: digit data collection and clock distribution 52011/02/18

6. U niversity of S cience and T echnology of C hina Design principle Clock distribution Serializer/Deserializer electro-optical/optical-electro FPGA-based TDC Coarse counter + fine counter High frequency clock phase shift Transmission delay calibration Echo-based calibration PMT readout QTC FPGA-based TDC 62011/02/18

7. U niversity of S cience and T echnology of C hina Clock distribution Offshore has the same frequency and fixed phase with onshore Onshore: Clock and data combined in the SerDes Bit stream sent to the offshore by optical transmitter Offshore: After long fiber, bit stream received by optical receiver Clock and data decoded in the SerDes Parallel data sent to FPGA as command or config Recovered clock as system clock after cleaned jitter by PLL 72011/02/18

8. U niversity of S cience and T echnology of C hina FPGA-based TDC Implemented in FPGA (Virtex4-10) Coarse counter: 40MHz system clock Fine counter: 400MHz divided into 4 phases, equals to 1.6GHz LSB=625ps Dynamic range=no limited 82011/02/18

9. U niversity of S cience and T echnology of C hina Transmission delay calibration Echo-based calibration Time recorded by FPGA-based TDC in Onshore ΔTdown = ΔTup= (T3 - T0 – ΔTs) / 2 92011/02/18

10. U niversity of S cience and T echnology of C hina Digitalization in Distributed Architecture Time over threshold scheme with linear charge-to-time conversion CLC101EF, designed for Super-Kamiokande, covers our requirement Input channel: 3 Dynamic range: 0.2~2500pC Gains: 3/channel (1:7:49) 0.2~51pC,1~357pC,5~2500pC Time resolution: 0.3ns Charge resolution: 0.2pC 10 chips have been purchased for prototype design 102011/02/18

11. U niversity of S cience and T echnology of C hina Detail of QTC Block diagram of QTCTiming chart for QTC operation In/Out signals of QTC PMT data rate: 50kHz/channel QTC dead time: 900ns Data loss: 0.968‰ (Poisson distribution) 112011/02/18

12. U niversity of S cience and T echnology of C hina Prototype design MasterPrototype (MP) Onshore function: clock, trigger, data processing Clock distribution Data transmission TDC based transmission delay calibration VME module SlaverPrototype (SP) Offshore function: FEE Clock distribution Data transmission PMT charge measurement PMT arrival time measurement USB module (test only) Version 1.0 Clock distribution and TDC verification Version 2.0 Readout electronics for prototype detector array 122011/02/18

13. U niversity of S cience and T echnology of C hina Schematic of Version 1.0 MasterPrototype (MP)SlaverPrototype (SP) GroupSerializerDeserializer 1SN65LVDS1023ASN65LVDS1224B 2DS92LV16 3TLK1521 4TLK1501 132011/02/18

14. U niversity of S cience and T echnology of C hina Evaluation boards of Version 1.0 MasterPrototype (MP) SlaverPrototype (SP) 142011/02/18

15. U niversity of S cience and T echnology of C hina SP MP Optical fiber 152011/02/18

16. U niversity of S cience and T echnology of C hina Clock distribution test 162011/02/18

17. U niversity of S cience and T echnology of C hina Clock distribution test GroupSerDes Cycle to cycle jitter/ ps Phase relationship TransmissionRecoveryJitter cleaned 1SN65LVDS1023A/1224B23.3047.1815.82Uncertainty 2DS92LV1623.2418.8016.78Fixed 3TLK152123.3621.6916.89Uncertainty 4TLK150123.3328.9216.50Uncertainty Test waveform in oscilloscope Blue: Transmission clock in MP Green: Recovered clock in SP Red: PLL output clock in SP 172011/02/18

18. U niversity of S cience and T echnology of C hina TDC test Spartan3A was used High speed clock ≤ 200MHz LSB=1.25ns DNL: -0.0544~+0.0558 LSB INL: -0.0037~+0.0800 LSB Virtex4-10 will be used in next version High speed clock ≤ 400MHz LSB=625ps 182011/02/18

19. U niversity of S cience and T echnology of C hina Calibration test In different lengths of fibers Resolution better than 1LSB Upgrade to 625ps in next version 192011/02/18

20. U niversity of S cience and T echnology of C hina Version 2.0 for prototype detector array 202011/02/18

21. U niversity of S cience and T echnology of C hina Sketch of Version 2.0 Q & T measurement: Time of Threshold- based QTC and FPGA-based TDC PMT signal preamplifiers QTC Calibration circuit Clock distribution and data transmission: SerDes and fiber SerDes PLL and clock fan out Others Power USB interface Upgrade to version 2 Virtex 4 instead of Spartan 3A 4 fiber channels for extending more FEEs Clock: synthesize clock from Ru OSC, distribute clock to FEE Trigger: collect hits, form and distribute trigger data processing: collect digit result 212011/02/18

22. U niversity of S cience and T echnology of C hina Progress FEE module under testing MP module under PCB layout 222011/02/18

23. U niversity of S cience and T echnology of C hina THANK YOU! 232011/02/18