1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Conditional-Sum-Adder Conditional-Sum-Adder Final Meeting: Silicon Ensemble Peter Kröger Course and contest 2005

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Core (Power Analyzer)

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Principle of Conditional-Sum-Adder - Partition of the addition into single bits - Parallel calculation of sum and carry-out for every single bit-group - Selection of right result by multiplexer-tree Function of Conditional-Sum-Cell Comparison of different non-redundant adders: Speed!

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Design Compiler - Compile Strategie Question: How can I get Design Compiler to work harder? 1) Strategy 1: Tighten Constraints => 10 percent can cause better results (i.e. set_max_delay) 2) Strategy 2: compile => compile -incremental -map_effort high (for small designs) 3) Strategy 3: DC Ultra => set_ultra optimization -true [force] BUT: much more time consuming during designing => costs Extra ordinary options are mostly not usefull in smaller designs!

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design Selected options for optimization 0.96 ns Netlist Silicon Ensemble Timing driven placement Timing driven routing Optimize:Timing Clock:H-tree-synthese Scaling down of core-size Higher row-utilization

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Spezielle Anwendungen des VLSI-Entwurfs Special applications of VLSI design List of all Values ValueName of design Best frequency :727.3 MHztiming9 Best area: 2.225 * 10 4 µm²timing9 Best power@50MHz: 17.6900 µWtiming9 Best PDP: 353.67 fJ timing9 Name of designer: Name of Design max. delay [ns] max. frequency f max [MHz] Power Dissipation @ f max [µW] PDP [fJ] Core-Area [µm²] Power Dissipation @ 50 MHz [µW] timing91.375727.3257.2124353.672.225 * 10 4 17.6900