1. FDR of the End-cap Muon Trigger Electronics 1/Mar./04 1 Slice Test (SLT) of TGC electronics Introduction Simulation Trigger part SLT Wire Wire and Signal Wire and Signal II Readout SLT Chikara Fukunaga (TMU)

2. FDR of the End-cap Muon Trigger Electronics 1/Mar./04 2 Introduction Trigger SLT (from 2001 to 2003) Comparison of the system output with one of the simulation Development of trigger simulation program was needed beside the test system (hardware/software) development Hardware inconsistency must be fixed in the following ASIC production if any, and this fix must be reflected in the simulation Readout SLT (2003) SLB ASIC  SSW  ROD

3. FDR of the End-cap Muon Trigger Electronics 1/Mar./04 3 Simulation Generation of Test Vectors with 3 different simulation programs; DICE (TGC Hit simulation on top of GEANT3) Output position information Digitize (position (r,  )  TGC channels = ASD outputs for wire and strip)  Test vectors t1me (trigger level 1 muon endcap) Trigger logic simulation SLB ASIC Hi-pT ASIC SL ASIC TTC simulation

4. FDR of the End-cap Muon Trigger Electronics 1/Mar./04 4 Trigger SLT (wire) in 2001 PPG: Pulse Pattern Generator 32bit width 64K depth for test vector inputs and TTC emulation (8 for wire emulation, 1 for TTC) Interrupt Register: Clock generation, trigger for PPG PS Board for forward: 8x16 channel PP ASICs, 2xSLB ASICs (type C of version 1) and 1 JRC (JTAG Routing Controller) CPLD SPP: mounts TTC emulator board no TTC facility used in this SLT Hi-pT board for forward: Hi-pT ASICs (version 2, Jan. 2001 submitted) HSC- C CI: HipT ASIC config., and HSC-CCI-PT4 for PP and SLB ASIC config. Test ROD: Japanese ROD with SH4 Instead of SL,ROD was used to record Hi-pT data

5. FDR of the End-cap Muon Trigger Electronics 1/Mar./04 5 Results of SLT2001 PP ASIC (masked at power on, remove them before actual use) - check with debug pin PS board (SLB ASIC) output was accessed by PT4 via LVDS Hi-pT board (Hi-pT ASIC) output was accessed by ROD After SLB-Hi-pT connection conflict has been sorted out, we get following results for Hi-pT wire output; Number of Tracks Number of Test vectors Number of Discrepancies 149920 2 0 336780

6. FDR of the End-cap Muon Trigger Electronics 1/Mar./04 6 Trigger SLT with wire and strip (2002) Control Software was complied with ATLAS online software DAQ-1 SLT using both wire (r) and strip (  ), r-  coincidence with SL Introduction of TTCvx-TTCvi-TTCrx chain PPG: 14 (8 for wire, 6 for strip) SPP: TTCrx board was mounted. SL: June 2001 version TOM: VME FIFO for SL data readout

7. FDR of the End-cap Muon Trigger Electronics 1/Mar./04 7 A SLB-ASIC problem for strip signal trigger If SLB ASIC of version 1 or 2 is used in the system, a software to compare the output with t1me must take into account the following known bug for trigger with strip ; Position of 0-th channel in SLB ASIC is shifted towards left in Pivot than Doubet.  =+1, position 1 for p T 

8. FDR of the End-cap Muon Trigger Electronics 1/Mar./04 8 Results of SLT2002 Comparison with t1me simulation at SL output Latency Number of TracksNumber of Test vectorsDiscrepancies found 1100000 2 0 ComponentsMeasurement (ns)Requirement(ns) ToF to TGC75 TGC25 ASD1025 Cable50 PP ASIC4350 SLB ASIC4975 LVDS (Tx,Rx)8375 Cable75 Hi-pT5575 G-link (Tx,Rx)10575 Fibre450 SL160175 Cable25 Total12051250

9. FDR of the End-cap Muon Trigger Electronics 1/Mar./04 9 The third trigger SLT (2003) New PS Boards for wire and strip New PP ASIC of 32 ch. Inputs (submitted in Jun.,’02) New SLB ASIC (version 2, submitted in Feb., ‘02) SPP with TTCrx, and then new SPP with TTCrq SSW for readout (but used for neither trigger nor control)

10. FDR of the End-cap Muon Trigger Electronics 1/Mar./04 10 Results of SLT2003 Some test vectors (used for previous SLT) gave discrepancies in low-p T trigger of wire signals with simulation, Problem of new PS board SLB ASIC version 2 has problem of I/O pads Only Outputs are effective from I/O pads We must isolate these pins from the board After the isolation, discrepancy in wire signals was dismissed. Results at SL output: Number of Tracks Number of Test vectors Discrepancies found 1100000 2 0 3 0

11. FDR of the End-cap Muon Trigger Electronics 1/Mar./04 11 Readout SLT in 2003 Readout Test in summer 2003 Test of data readout with SLB ASIC-SSW-(Test-)ROD chain Consistency of Bunch count (BCID) and Event count (L1ID) in all the modules With Two Test Pulse Generators ASD (TTCvi Test pulse trigger   TTCrq  SLB  PP ASIC  ASD) All on/off, Pulse H: 16 levels SLB ASIC (TTCvi Test pulse trigger   TTCrq  SLB) (TPP register 160bit and input from PP ASIC masked) Test pattern (individual bits) Delay

12. FDR of the End-cap Muon Trigger Electronics 1/Mar./04 12 Test of Readout with Test pulse Readout test with SLB test pulse pattern: Depth of L1 buffer in SLB can be adjusted with sequence of Set SLB Test Pulse Pattern (TPP), and Issue of Test pulse trigger at TTCvi, and Generation of L1A after some clock Readout test with ASD or ASD Emulator Check for Test Pulse Trigger from PP ASIC towards ASD Set of SLB input masks to generate a desired pattern

13. FDR of the End-cap Muon Trigger Electronics 1/Mar./04 13 Results of Readout SLT 5 Test patterns were used for readout test (Test pattern set using JTAG has taken long time) All 0: All channel no hit All 1: All channel hit Even: Hits in all even channels Odd: Hits in all odd channels Header: A pattern with two tracks We have confirmed that readout worked fine for all the channels with all the patterns by two Test pulse pattern generations (SLB ASIC and ASD-Emulator) We found also BCID and L1ID were matched uniquely in all the modules (PS board, SSW, SL, Test-ROD).