1. © 2008, Renesas Technology America, Inc., All Rights Reserved 1 Module Introduction Purpose  This training module provides an overview of the different timers that H8S MCUs provide for tasks such as counting, input capture, output compare, PWM output, etc. Objective  Understand the design, features and operation of the 8-bit timer, Watchdog Timer (WDT), 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), and motor management timer (MMT). Content  24 pages  4 questions Learning Time  45 minutes

2. © 2008, Renesas Technology America, Inc., All Rights Reserved 2 8-bit Timer Up to four channels of 8-bit timer  Uses internal or external clock  Provides two compare-match signals  Two channels can be cascaded to get a 16-bit timer  Can generate A/D converter conversion-start trigger  Can be put into Module Stop mode to save power Applications  Generate counter reset, interrupt requests  Generate pulse output with an arbitrary duty cycle using compare-match signal with two registers

3. © 2008, Renesas Technology America, Inc., All Rights Reserved 3 8-Bit Timer Circuit Clock Select Control Logic Comparator A0Comparator A1 TCNT0TCNT1 Comparator B0Comparator B1 TCORA0TCORA1 TCORB0TCORB1 TCSR0TCSR1 TCR1 TCLKA TCLKC f/8 f/64 f/8192 Timer I/O TCLKA TCLKC Interrupt Signals CMIA0 CMIB0 CMIA1 / CMIB1 OVI0 / OVI1 Clock 1 Clock 0 TCR0

4. © 2008, Renesas Technology America, Inc., All Rights Reserved 4 Examples of Timer Operation Free- Running Timer PWM Pulse Output

5. © 2008, Renesas Technology America, Inc., All Rights Reserved 5 Watchdog Timer Generates an internal reset signal or an internal NMI interrupt signal if a system crash occurs Has security feature that minimizes probability of inadvertent, disabling writes to WDT registers Can use eight (WDT_0) or sixteen (WDT_1) counter input clocks Can be switched from Watchdog Timer mode to Interval Timer mode for use as an interval timer when watchdog function isn’t needed Watchdog Timer mode  If WDT counter overflows, an internal reset or an internal NMI interrupt is generated  When MCU is selected to be internally reset at WDT counter overflow, signal at the RESO pin goes low when overflow occurs Interval Timer mode  If WDT counter overflows, an internal timer interrupt (WOVI) is generated

6. © 2008, Renesas Technology America, Inc., All Rights Reserved 6 Watchdog Timer Circuit Internal Bus Bus Interface Module Bus TCNTTCSR Clock Select Interrupt Control Reset Control WOV1 Internal NMI RESET Internal reset Overflow Clock Internal Clock Source Ø/2, Ø/64 Ø/128, Ø/512 Ø/2048, Ø/8192 Ø/32768, Ø/131072 Øsub/2, Øsub/4 Øsub/8, Øsub/16 Øsub/32, Øsub/64 Øsub/128, Øsub/256

8. © 2008, Renesas Technology America, Inc., All Rights Reserved 8 16-bit Timer Pulse Unit Up to six channels of 16-bit TPU  Can use multiple internal or external clock signals  Input capture function detects rising edge, falling edge, or both  Provides 0, 1, or toggle output at compare-match  Counter can be cleared by compare-match or input capture  PWM output waveform can be produced with an arbitrary duty cycle  Phase counting mode can be set independently for each channel  Allows automatic transfer of register data using data transfer controller (DTC) or DMA controller (DMAC)  Can generate programmable pulse generator (PPG) output trigger, A/D conversion-start trigger

9. © 2008, Renesas Technology America, Inc., All Rights Reserved 9 Circuit for 16-bit TPU Control Logic for Channels 3, 4, 5 TIORH TMDRTCR TIORL TIERTSR TCNT TGRA TGRB TGRC TGRD TIOR TMDRTCR TIERTSR TCNT TGRA TGRB TIOR TMDRTCR TIERTSR TCNT TGRA TGRB Control Logic TSTRTSYR Bus Interface TIOR TMDRTCR TIERTSR TCNT TGRA TGRB TIOR TMDRTCR TIERTSR TCNT TGRA TGRB TIORH TMDRTCR TIORL TIERTSR TCNT TGRA TGRB TGRC TGRD Channel 0 Channel 1Channel 2Channel 5Channel 4Channel 3 Control Logic for Channels 0, 1, 2

11. © 2008, Renesas Technology America, Inc., All Rights Reserved 11 Free-Running/Periodic Counter Free Running Counter Operation Periodic Counter Operation Time CST bit TGF H’0000 TGR Flag cleared by software or DTC activation Counter cleared by TGR compare-match TCNT value Time CST bit TCFV H’0000 H’FFFF TCNT value

12. © 2008, Renesas Technology America, Inc., All Rights Reserved 12 Output-Compare Mode Time TIOCA TIOCB H’0000 H’FFFF TCNT value No change 1 output 0 output TGRA TGRB Time TIOCA TIOCB H’0000 H’FFFF TCNT value Toggle output TGRA TGRB Example of 0 Output / 1 Output Example of Toggle Output

13. © 2008, Renesas Technology America, Inc., All Rights Reserved 13 Input-Capture Mode TCNT value H’0180 H’0160 H’0010 H’0005 H’0000 TIOCA TGRA TIOCB TGRB H’0005H’0160H’0010 H’0180 Example of Input Capture Operation

14. © 2008, Renesas Technology America, Inc., All Rights Reserved 14 Phase Counting, Modes 1 and 2 Calculate the amount of rotation, as well as the direction of rotation of the motor Calculate the amount of rotation when the second sensor changes value

15. © 2008, Renesas Technology America, Inc., All Rights Reserved 15 Phase Counting, Modes 3 and 4 Checks which sensor generates data Checks the correlation between two sensors

17. © 2008, Renesas Technology America, Inc., All Rights Reserved 17 Programmable Pulse Generator Can generate an arbitrary waveform based on a memory- mapped image of the waveform stored in memory  Uses the 16-bit TPU as a time base and operates with data transfer controller (DTC) or DMA controller (DMAC)  Can output up to 8-bit or 16-bit data, with output enabled on a bit-by-bit basis  Pulses can be generated in groups of four bits, and up to four groups are supported, normal or inverted  Output trigger signals can be selected in 4-bit groups using compare-match signals  Non-overlap margin can be provided between pulse outputs  Can be put into Module Stop mode to save power

18. © 2008, Renesas Technology America, Inc., All Rights Reserved 18 16-bit TPU and PPG Internal Data Bus NDRB NDRA PBDR PADR NDERB TPCRTPMR NDERA 16-bit TPU Compare-Match Signals TP 12 -TP 15 TP 8 -TP 11 TP 4 -TP 7 TP 0 -TP 3 Pulse O/P pins group 3 Pulse O/P pins group 2 Pulse O/P pins group 1 Pulse O/P pins group 0 TPMR:TPC output mode register TPCR:TPC output control register NDERA: Next data enable register A NDERB: Next data enable register B NDRB:Next data register B NDRA:Next data register A PBDR:Port B data register PADR:Port A data register

19. © 2008, Renesas Technology America, Inc., All Rights Reserved 19 Operation of TPU and PPG TCNT Value Time Compare-Matches TCNT 80 C0 406020301018088880C040 80 C0 406020301018088880C000 NDRB PBDR TP13 TP15 TP14 TP11 TP12

20. © 2008, Renesas Technology America, Inc., All Rights Reserved 20 Motor Management Timer MMT produces 6-phase complimentary PWM with non-overlap times Dead times can be generated by dedicated timers Toggle output synchronized with PWM period Counter clearing on external signal DTC or DMAC activated On-chip A/D converter started Output-off functionality  PWM halted by external signal  PWM halted when oscillator stops Can be halted in Module Standby mode to save power

21. © 2008, Renesas Technology America, Inc., All Rights Reserved 21 MMT Circuit TBRUTBRVTSR Magnitude Comparators TGRUU TGRU TGRUD TGRVU TGRV TGRVDTGRWU TGRWTGRWD +2Td +Td TCNT TMDR TCNT Comparators TPDR TPBRTDDR Comparators TDCNT0 Control Circuit Pf to Pf / 1024 PCIO PUOA PUOB PVOA PVOB PWOA PWOB ADC start trigger +2Td x2 TPDR Compare Match Interrupt 2Td Compare-Match Interrupt TBRW

22. © 2008, Renesas Technology America, Inc., All Rights Reserved 22 MMT 6-phase PWM Output TGRUU TGRUD U U’ TGRU TGRVU TGRVD TGRV TGRWU TGRWD TGRW V V’ W W’ TCNT 2Td Td: Dead Time Buffer registers General registers TBRU TBRV TBRW

24. © 2008, Renesas Technology America, Inc., All Rights Reserved 24 Module Summary  8-bit timer  16-bit TPU  WDT  PPG  MMT To get detailed information about all MCU solutions from Renesas including H8S MCUs. Please visit our website: www.renesas.com