1. MSc - Microprocessors
Dr. Konstantinos Tatas

2. Useful Information Instructor: Lecturer K. Tatas
Office hours: TBA
Lecture periods/week: 3
Duration: 10 weeks
ECTS: 7 (175 hours)

3. Course Objectives By the end of the course students should be able to:
Evaluate the complex trade-offs involved in embedded system design
Write detailed embedded system requirements and specification documents
Write executable specifications using UML/SystemC
Develop applications using ARM Developer Suite
Write efficient ARM assembly and C programs in ARM and Thumb mode
Analyze program performance using traces
Use code transformations to improve performance/code size/power consumption.

4. Course Outline (1/2)
Week 1: Introduction to embedded systems – Embedded microprocessor evolution – Design metrics and constraints (performance, power, cost, time-to-market) and design optimization challenges - Distributed and Real-time systems
Week2: Key embedded system technologies – Integrated Circuit technology – Microprocessor technology – CAD tool technology – Sensor technology
Week 3: Embedded system specification and modeling – Object-oriented specification (UML/C++/SystemC) – Assignment 1
Week 4: Computer Architecture – Instruction sets – RISC vs. CISC – pipelining - The ARM microprocessor architecture - ARM assembly – ARM mode – Thumb mode - ARM and Thumb instruction set - ARM conditional execution
Week 5: Processor I/O – Serial I/O – Busy/wait I/O – Interrupts – Exceptions – Traps – ARM memory mapped I/O - Caches – Memory Management Units – Protection Units – ARM cache and MMU – Assignment 2

5. Course Outline (2/2) Week 6: Assignment 1
Week 7: Programme design and analysis – DFGs – CDFGs – Compilers – Assemblers – Linkers – Basic compiler optimizations/code transformations – Measuring programme speed – Trace-driven performance analysis – Energy optimization – programme size optimization
Week 8: Code transformations – Loop unrolling – loop merging – loop tiling – performance optimizing transformations
Week 9: Test
Week 10: Assignment 2

6. Course Assessment Final exam: 40% Coursework: 60% Assignment 1: 15%
Quizzes: 10%
Test: 10%
Lab exercises: 10%

7. References Books W. Wolf, “Computers as Components”
W. Wolf, “High-Performance Embedded Computing”
H. Kopetz, “Real-Time Systems: Design Principles for Distributed Embedded Applications”
S. Furber, “ARM System-on-Chip Architecture”
P. Panda, “Memory Issues in Embedded Systems-on-Chip”
F. Vahid and T. Givargis, “Embedded System Design: A Unified Hardware/Software Introduction”
F. Catthoor, “Data Access and Storage Management for Embedded Programmable Processors”

8. Microprocessors for Embedded systems
Computing systems are everywhere
Most of us think of “desktop” computers
PC’s
Laptops
Mainframes
Servers
But there’s another type of computing system
Far more common...

9. Embedded systems overview
Embedded computing systems
Computing systems embedded within electronic devices
Hard to define. Nearly any computing system other than a desktop computer
Billions of units produced yearly, versus millions of desktop units
Perhaps 50 per household and per automobile
Computers are in here...
and here...
and even here...
Lots more of these, though they cost a lot less each.

10. A “short list” of embedded systems
Anti-lock brakes
Auto-focus cameras
Automatic teller machines
Automatic toll systems
Automatic transmission
Avionic systems
Battery chargers
Camcorders
Cell phones
Cell-phone base stations
Cordless phones
Cruise control
Curbside check-in systems
Digital cameras
Disk drives
Electronic card readers
Electronic instruments
Electronic toys/games
Factory control
Fax machines
Fingerprint identifiers
Home security systems
Life-support systems
Medical testing systems
Modems
MPEG decoders
Network cards
Network switches/routers
On-board navigation
Pagers
Photocopiers
Point-of-sale systems
Portable video games
Printers
Satellite phones
Scanners
Smart ovens/dishwashers
Speech recognizers
Stereo systems
Teleconferencing systems
Televisions
Temperature controllers
Theft tracking systems
TV set-top boxes
VCR’s, DVD players
Video game consoles
Video phones
Washers and dryers
And the list goes on and on

11. Some common characteristics of embedded systems
Single-functioned
Executes a single program, repeatedly
Tightly-constrained
Low cost, low power, small, fast, etc.
Reactive and real-time
Continually reacts to changes in the system’s environment
Must compute certain results in real-time without delay

12. An embedded system example – Digital camera
Microcontroller
CCD preprocessor
Pixel coprocessor
A2D
D2A
JPEG codec
DMA controller
Memory controller
ISA bus interface
UART
LCD ctrl
Display ctrl
Multiplier/Accum
Digital camera chip
lens
CCD
Single-functioned -- always a digital camera
Tightly-constrained -- Low cost, low power, small, fast
Reactive and real-time -- only to a small extent

13. Embedded Software Development Requires as Much/More Design Effort Than Hardware

14. A System-on-a-Chip: Example
Courtesy: Philips

15. Design at a crossroad System-on-a-Chip
RAM
500 k Gates FPGA
+ 1 Gbit DRAM
Preprocessing
Multi-
Spectral
Imager mC
system
+2 Gbit
DRAM
Recog-
nition
Analog
64 SIMD Processor
Array + SRAM
Image Conditioning
100 GOPS
Embedded applications where cost, performance, and energy are the real issues!
DSP and control intensive
Mixed-mode
Combines programmable and application-specific modules
Software plays crucial role

16. Disciplines involved in Embedded System Design
Digital System Design
Software Design
Analog/Mixed-Signal/RF System Design
Operating Systems
Microprocessors/Computer Architecture
Verification
Testing
etc

17. Languages traditionally used in Embedded System Design
Software design
C/C++
Java
Assembly
Verification
VHDL/Verilog
SystemVerilog
Tcl/tk
Vera
Specification/modeling
UML
SDL
C/C++
Hardware design
VHDL
Verilog

18. Design challenge – optimizing design metrics
Obvious design goal:
Construct an implementation with desired functionality
Key design challenge:
Simultaneously optimize numerous design metrics
Design metric
A measurable feature of a system’s implementation
Optimizing design metrics is a key challenge

19. Design challenge – optimizing design metrics
Common metrics
Unit cost: the monetary cost of manufacturing each copy of the system, excluding NRE cost
NRE cost (Non-Recurring Engineering cost): The one-time monetary cost of designing the system
Size: the physical space required by the system
Performance: the execution time or throughput of the system
Power: the amount of power consumed by the system
Flexibility: the ability to change the functionality of the system without incurring heavy NRE cost

20. Design challenge – optimizing design metrics
Common metrics (continued)
Time-to-prototype: the time needed to build a working version of the system
Time-to-market: the time required to develop a system to the point that it can be released and sold to customers
Maintainability: the ability to modify the system after its initial release
Correctness, safety, many more

21. Design metric competition -- improving one may worsen others
Size
Performance
Power
NRE cost
Expertise with both software and hardware is needed to optimize design metrics
Not just a hardware or software expert, as is common
A designer must be comfortable with various technologies in order to choose the best for a given application and constraints
Microcontroller
CCD preprocessor
Pixel coprocessor
A2D
D2A
JPEG codec
DMA controller
Memory controller
ISA bus interface
UART
LCD ctrl
Display ctrl
Multiplier/Accum
Digital camera chip
lens
CCD

22. Time-to-market: a demanding design metric
Time required to develop a product to the point it can be sold to customers
Market window
Period during which the product would have highest sales
Average time-to-market constraint is about 8 months
Delays can be costly
Revenues ($)
Time (months)

23. Losses due to delayed market entry
On-time Delayed
entry entry
Peak revenue
Peak revenue from delayed entry
Market rise
Market fall W 2W
Time D
On-time
Delayed
Revenues ($)
Simplified revenue model
Product life = 2W, peak at W
Time of market entry defines a triangle, representing market penetration
Triangle area equals revenue
Loss
The difference between the on-time and delayed triangle areas

24. Losses due to delayed market entry (cont.)
Area = 1/2 * base * height
On-time = 1/2 * 2W * W
Delayed = 1/2 * (W-D+W)*(W-D)
Percentage revenue loss = (D(3W-D)/2W2)*100%
Try some examples
On-time Delayed
entry entry
Peak revenue
Peak revenue from delayed entry
Market rise
Market fall W 2W
Time D
On-time
Delayed
Revenues ($)
Lifetime 2W=52 wks, delay D=4 wks
(4*(3*26 –4)/2*26^2) = 22%
Lifetime 2W=52 wks, delay D=10 wks
(10*(3*26 –10)/2*26^2) = 50%
Delays are costly!

25. The performance design metric
Widely-used measure of system, widely-abused
Clock frequency, instructions per second – not good measures
Digital camera example – a user cares about how fast it processes images, not clock speed or instructions per second
Latency (response time)
Time between task start and end
e.g., Camera’s A and B process images in 0.25 seconds
Throughput
Tasks per second, e.g. Camera A processes 4 images per second
Throughput can be more than latency seems to imply due to concurrency, e.g. Camera B may process 8 images per second (by capturing a new image while previous image is being stored).
Speedup of B over S = B’s performance / A’s performance
Throughput speedup = 8/4 = 2

26. Three key embedded system technologies
Technology
A manner of accomplishing a task, especially using technical processes, methods, or knowledge
Three key technologies for embedded systems
Processor technology
IC technology
Design technology

27. Processor technology
The architecture of the computation engine used to implement a system’s desired functionality
Processor does not have to be programmable
“Processor” not equal to general-purpose processor
Controller
Datapath
Controller
Datapath
Controller
Datapath
Control
logic and State register
Register
file
Control logic and State register
Registers
Control
logic
index
total
Custom
ALU
State register +
General
ALU IR PC IR PC
Data
memory
Data
memory
Program memory
Data
memory
Program memory
Assembly code for:
total = 0
for i =1 to …
Assembly code for:
total = 0
for i =1 to …
General-purpose (“software”)
Application-specific
Single-purpose (“hardware”)

28. Processor technology
Processors vary in their customization for the problem at hand
total = 0
for i = 1 to N loop
total += M[i]
end loop
Desired functionality
General-purpose processor
Application-specific processor
Single-purpose processor

29. General-purpose processors
Datapath IR PC
Register
file
General
ALU
Controller
Program memory
Assembly code for:
total = 0
for i =1 to …
Control
logic and State register
Data
memory
Programmable device used in a variety of applications
Also known as “microprocessor”
Features
Program memory
General datapath with large register file and general ALU
User benefits
Low time-to-market and NRE costs
High flexibility
“Pentium” the most well-known, but there are hundreds of others

30. Single-purpose processors
Datapath
Controller
Control logic
State register
Data
memory
index
total +
Digital circuit designed to execute exactly one program
a.k.a. coprocessor, accelerator or peripheral
Features
Contains only the components needed to execute a single program
No program memory
Benefits
Fast
Low power
Small size

31. Application-specific processors
Datapath IR PC
Registers
Custom
ALU
Controller
Program memory
Assembly code for:
total = 0
for i =1 to …
Control
logic and State register
Data
memory
Programmable processor optimized for a particular class of applications having common characteristics
Compromise between general-purpose and single-purpose processors
Features
Program memory
Optimized datapath
Special functional units
Benefits
Some flexibility, good performance, size and power

32. IC technology
The manner in which a digital (gate-level) implementation is mapped onto an IC
IC: Integrated circuit, or “chip”
IC technologies differ in their customization to a design
IC’s consist of numerous layers (perhaps 10 or more)
IC technologies differ with respect to who builds each layer and when
source
drain
channel
oxide
gate
Silicon substrate
IC package IC

33. IC technology Design Approaches
Custom
Standard Cells
Compiled Cells
Macro Cells
Cell-based
Pre-diffused
(Gate Arrays)
Pre-wired
(FPGA's)
Array-based
Semicustom
IC Technology Implementation Approaches

34. Full-custom design
All layers are optimized for an embedded system’s particular digital implementation
Placing transistors
Sizing transistors
Routing wires
Benefits
Excellent performance, small size, low power
Drawbacks
High NRE cost (e.g., $300k), long time-to-market

35. The Custom Approach
Intel 4004
Courtesy Intel

36. Transition to Automation and Regular Structures
Intel 4004 (‘71)
Intel 8080
Intel 8085
Intel 8286
Intel 8486
Courtesy Intel

38. IC technology Design Approaches
IC Technology Implementation Approaches
Custom
Semicustom
Cell-based
Array-based
Standard Cells
Pre-diffused
Pre-wired
Macro Cells
Compiled Cells
(Gate Arrays)
(FPGA's)

39. Semi-custom Lower layers are fully or partially built Benefits
Designers are left with routing of wires and maybe placing some blocks
Benefits
Good performance, good size, less NRE cost than a full-custom implementation (perhaps $10k to $100k)
Drawbacks
Still require weeks to months to develop

40. Cell-based Design (or standard cells)
Routing channel
requirements are
reduced by presence
of more interconnect
layers

41. Standard Cell — Example
[Brodersen92]

42. Standard Cell - Example
3-input NAND cell
(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time

43. IC technology Design Approaches
IC Technology Implementation Approaches
Custom
Semicustom
Cell-based
Array-based
Standard Cells
Pre-diffused
Pre-wired
Macro Cells
Compiled Cells
(Gate Arrays)
(FPGA's)

44. Programmable Logic Devices
All layers (diffusion, polysilicon, [multi-] metal) may exist
Designers can purchase an IC
Connections on the IC are either created or destroyed to implement desired functionality
Field-Programmable Gate Array (FPGA) and recently Gate Arrays are very popular
Benefits
Low NRE costs, almost instant IC availability
Drawbacks
Bigger, expensive (perhaps $30 per unit), power hungry, slower

45. Gate Array — Sea-of-gates
Uncommited
Cell
Committed
Cell (4-input NOR)

46. Sea-of-gate Primitive Cells
Using oxide-isolation
Using gate-isolation

47. Sea-of-gates Random Logic Memory Subsystem LSI Logic LEA300K
(0.6 mm CMOS)

48. Prewired Arrays
Classification of prewired arrays (or field-programmable devices):
Based on Programming Technique
Fuse-based (program-once)
Non-volatile EPROM based
RAM based
Programmable Logic Style
Array-Based
Look-up Table
Programmable Interconnect Style
Channel-routing
Mesh networks

49. Altera MAX
From Smith97

50. Altera MAX Interconnect Architecture
column channel
row channel
LAB2
PIA
LAB1
LAB6 t
LAB
Array-based
(MAX )
Mesh-based
(MAX 9000)

51. LUT-Based Logic Cell Xilinx 4000 Series 4 C ....C xx xxxx xxxx xxxx D1 4 xx
xxxx
xxxx
xxxx D
Bits
xxxx 4
Logic
control xx D xx
function xx x xx 3 xx x of D xx 2
xxx D 1
Logic xx
function x xx x x of x x
xxx F 4
Bits
xxxx
Logic xx
control F xx 3
function xx xx xx x x F of xx 2
xxx F 1 xx x xx
xxxxx H x x P
Multiplexer Controlled
Xilinx 4000 Series
by Configuration Program

52. Array-Based Programmable Wiring
Input/output pin
Programmed interconnection
Interconnect
Point
Horizontal
tracks
Cell
Vertical tracks

53. Transistor Implementation of Mesh
Courtesy Dehon and Wawrzyniek

54. RAM-based FPGA
Xilinx XC4000ex

55. Design Technology
The manner in which we convert our concept of desired system functionality into an implementation
Compilation/
Synthesis
Libraries/ IP
Test/
Verification
System
specification
System
synthesis
Hw/Sw/ OS
Model simulat./
checkers
Compilation/Synthesis: Automates exploration and insertion of implementation details for lower level.
Behavioral
specification
Behavior
synthesis
Cores
Hw-Sw
cosimulators
Libraries/IP: Incorporates pre-designed implementation from lower abstraction level into higher level. RT
specification RT
synthesis RT
components
HDL simulators
Test/Verification: Ensures correct functionality at each level, thus reducing costly iterations between levels.
Logic
specification
Logic
synthesis
Gates/
Cells
Gate
simulators
To final implementation

56. The co-design ladder In the past:
Hardware and software design technologies were very different
Recent maturation of synthesis enables a unified view of hardware and software
Hardware/software “codesign”
Implementation
Assembly instructions
Machine instructions
Register transfers
Compilers
(1960's,1970's)
Assemblers, linkers
(1950's, 1960's)
Behavioral synthesis
(1990's)
RT synthesis
(1980's, 1990's)
Logic synthesis
(1970's, 1980's)
Microprocessor plus program bits: “software”
VLSI, ASIC, or PLD implementation: “hardware”
Logic gates
Logic equations / FSM's
Sequential program code (e.g., C, VHDL)
The choice of hardware versus software for a particular function is simply a tradeoff among various design metrics, like performance, power, size, NRE cost, and especially flexibility; there is no fundamental difference between what hardware or software can implement.

57. Independence of processor and IC technologies
Basic tradeoff
General vs. custom
With respect to processor technology or IC technology
The two technologies are independent
General-purpose
processor
ASIP
Single-
purpose
Semi-custom
PLD
Full-custom
General,
providing improved:
Customized,
Power efficiency
Performance
Size
Cost (high volume)
Flexibility
Maintainability
NRE cost
Time- to-prototype
Time-to-market
Cost (low volume)

58. Design Decision Trade-offs

59. Generalised Design Flow

60. Architecture ReUse Silicon System Platform Has been successful in PC’s
Flexible architecture for hardware and software
Specific (programmable) components
Network architecture
Software modules
Rules and guidelines for design of HW and SW
Has been successful in PC’s
Dominance of a few players who specify and control architecture
Application-domain specific (difference in constraints)
Speed (compute power)
Dissipation
Costs
Real / non-real time data

61. Platform-Based Design
“Only the consumer gets freedom of choice;
designers need freedom from choice”
(Orfali, et al, 1996, p.522)
A platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developer
New platforms will be defined at the architecture-micro-architecture boundary
They will be component-based, and will provide a range of choices from structured-custom to fully programmable implementations
Key to such approaches is the representation of communication in the platform model
Source:R.Newton

62. Platform-based Design – System-on-Chip
Use of predefined Intellectual Property (IP)
A platform-based system consists of a RISC processor, memories, busses and a common language
Platform-based design poses the problem of partitioning a solution between hardware (HDL) and software (programming processors)

63. Platforms Enable Simplified SoC Design
Customer demands
Fast turn-around time
Easy access to pre-qualified building blocks
Web enabled
Design technology
Core platforms
‘Big’ IP
Emerging SoC bus standards
Embedded software
HW/SW co-verification
Far Peripherals
Near Peripherals
Core

64. And Automation of IP Selection & Integration

65. Heterogeneous Programmable Platforms
FPGA Fabric
Embedded memories
Embedded PowerPc
Hardwired multipliers
Xilinx Vertex-II Pro
High-speed I/O

66. Xilinx’s products

67. Xilinx’s products

68. Comparison of CMOS design methods
NRE
Unit Cost
Power Dissipation
Complexity of Implementation
Time-to-Market
Performance
Flexibility
μProcessor/DSP
low
medium
high
PLA
FPGA
Gate/Array
Cell Based
Custom Design
Very high
Platform Based
Low/medium
Medium/low

69. Impact of Implementation Choices
Energy Efficiency (in MOPS/mW)
Flexibility (or application scope)
0.1-1
1-10
10-100
None
Fully
flexible
Somewhat
Hardwired custom
Configurable/Parameterizable
Domain-specific processor
(e.g. DSP)
Embedded microprocessor

70. Design Economics (1)
The selling price of an IC Stotal=Ctotal/(1-m), Ctotal is manufacturing cost for a single IC, m desired profit margin
Costs for produce an IC
Non-recurring engineering costs (NREs)
Recurring engineering costs
Fixed costs

71. Design Economics (2) Non-recurring engineering costs (NREs)
Engineering design cost
Prototype manufacturing cost
Recurring costs
Process
Package
Test

72. NRE and unit cost metrics
Costs:
Unit cost: the monetary cost of manufacturing each copy of the system, excluding NRE cost
NRE cost (Non-Recurring Engineering cost): The one-time monetary cost of designing the system
total cost = NRE cost unit cost * # of units
per-product cost = total cost / # of units
= (NRE cost / # of units) + unit cost
Example
NRE=$2000, unit=$100
For 10 units
total cost = $ *$100 = $3000
per-product cost = $2000/10 + $100 = $300
Amortizing NRE cost over the units results in an additional $200 per unit

73. NRE and unit cost metrics
Compare technologies by costs -- best depends on quantity
Technology A: NRE=$2,000, unit=$100
Technology B: NRE=$30,000, unit=$30
Technology C: NRE=$100,000, unit=$2
But, must also consider time-to-market

74. Wafer and die cost
Die yield: number of good dies/total number of dies

75. Example Assuming: Calculate the minimum shelf price of the chip
20 engineers are employed full-time for a year with a $50,000/year average salary
Additional 200,000 overhead costs of which 100,000 for total testing
A wafer cost of $200 per wafer
A $2 packaging cost per chip
10 dies/wafer
70% die yield
98% final test yield
A market for 100,000 items
Calculate the minimum shelf price of the chip

76. Design productivity exponential increase
100,000
10,000
1,000
100
(K) Trans./Staff – Mo.
Productivity 10 1
0.1
0.01
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009
Exponential increase over the past few decades

77. The growing design-productivity gap
Moore’s Law:
Standard cell density and speed
Design Productivity Crisis (SRC 1997)
Potential Design Complexity and Designer Productivity
10,000
1,000
100
1,000
100 10 1
0.1
0.01
0.001
10,000
100,000,000
0.01
0.1 1 10
100
1,000
10,000
Equivalent Added Complexity
Gates
Clock
Logic Tr. / Chip
Tr. / S.M.
58% / yr compounded
Complexity Growth Rate
Density (Kgates / mm2) ASIC clock (MHz)
Logic Transistor per Chip ( M )
Productivity ( K) Trans./Staff – Mo.
21% / yr compounded
Productivity Growth Rate x
2001
2003
2005
2007
2009
2011
2013
2015
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009

78. Design productivity gap
1981 leading edge chip required 100 designer months
10,000 transistors / 100 transistors/month
2002 leading edge chip requires 30,000 designer months
150,000,000 / transistors/month
Designer cost increase from $1M to $300M
While designer productivity has grown at an impressive rate over the past decades, the rate of improvement has not kept pace with chip capacity

79. The mythical man-month
The situation is even worse than the productivity gap indicates
In theory, adding designers to team reduces project completion time
In reality, productivity per designer decreases due to complexities of team management and communication
In the software community, known as “the mythical man-month” (Brooks 1975)
At some point, can actually lengthen project completion time! (“Too many cooks”)
10000
20000
30000
40000
50000
60000 10 20 30 40 43 24 19 16 15 18 23
Team
Individual
Months until completion
Number of designers
1M transistors, 1 designer=5000 trans/month
Each additional designer reduces for 100 trans/month
So 2 designers produce 4900 trans/month each

80. Summary Embedded systems are everywhere
Key challenge: optimization of design metrics
Design metrics compete with one another
A unified view of hardware and software is necessary to improve productivity
Three key technologies
Processor: general-purpose, application-specific, single-purpose
IC: Full-custom, semi-custom, PLD
Design: Compilation/synthesis, libraries/IP, test/verification

81. Real-time and distributed systems
Dr. Konstantinos Tatas

82. What is real-time? Is there any other kind?
A real-time computer system is a computer system where the correctness of the system behavior depends not only on the logical results of the computations, but also on the physical time when these results are produced.
By system behavior we mean the sequence of outputs in time of a system.

83. Real-time means reactive
A real-time computer system must react to stimuli from its environment
The instant when a result must be produced is called a deadline.
If a result has utility even after the deadline has passed, the deadline is classified as soft, otherwise it is firm.
If severe consequences could result if a firm deadline is missed, the deadline is called hard.
Example: Consider a traffic signal at a road before a railway crossing. If the traffic signal does not change to red before the train arrives, an accident could result.

84. Reliability
The Reliability R(t) of a system is the probability that a system will provide the specified service until time t, given that the system was operational at the beginning (t-t0)
The probability that a system will fail in a given interval of time is expressed by the failure rate, measured in FITs (Failure In Time).
A failure rate of 1 FIT means that the mean time to a failure (MTTF) of a device is 10^9 h, i.e., one failure occurs in about 115,000 years.
If a system has a constant failure rate of λ failures/h, then the reliability at time t is given by
R(t)= exp(-λ(t-to))
MTTF = 1/λ

85. Example
What must be the system failure rate so that 99% of the systems in the field work reliably for the first 100,000 hours?

86. Safety

87. Maintainability

88. Name some hard, firm and soft deadline embedded systems

89. Example
an automotive company produces 2,000,000 electronic engine controllers of a special type.
The following design alternatives are discussed
(a) Construct the engine control unit as a single SRU with the application software in Read Only Memory (ROM).The production cost of such a unit is $250. In case of an error, the complete unit has to be replaced.
(b) Construct the engine control unit such that the software is contained in a ROM that is placed on a socket and can be replaced in case of a software error. The production cost of the unit without the ROM is $248. The cost of the ROM is $5.
(c) Construct the engine control unit as a single SRU where the software is loaded in a Flash EPROM that can be reloaded. The production cost of such a unit is $255.
The labor cost of repair is assumed to be $50 for each vehicle. (It is assumed to be the same for each one of the three alternatives).
Calculate the cost of a software error for each one of the three alternative designs if 300,000 cars have to be recalled because of the software error (example in Sect ).
Which one is the lowest cost alternative if only 1,000 cars are affected by a recall?

90. Distributed RT system model
From the POV of an outside observer, a real-time (RT) system can be decomposed into three communicating subsystems:
a controlled object (the physical subsystem, the behavior of which is governed by the laws of physics),
a “distributed” computer subsystem (the cyber system, the behavior of which is governed by the programs that are executed on digital computers)
a human user or operator
The distributed computer system consists of computational nodes that interact by the exchange of messages.
A computational node can host one or more computational components.

91. Event-Triggered Control Versus Time-Triggered Control