1. Memory interface Memory is a device to store data
To interfacing with memories, there must be:
address bus, data bus and control (chip enable, output enable)
To study memory interface, we must learn how to connect memory chips to the microprocessor and how to write/read data from the memory
Different kinds of memory chips will also be introduced

2. Memory Knowing memory is becoming more important
Your mobile devices do not have a harddisk but they have memory
IPad or other tablet computer has no harddisk!
But still very powerful!
Latest trend SSD (solid state drive) – a data storage device that uses solid-state memory to store data similar to a traditional harddisk
SSD is now rather expensive
A 64GB SSD is in the range HKD1000

3. Block diagram of a memory interface
Address in Hex
Content
FFFF
Data
Control signals
Include enable (chip select)
, read/write
0000

4. Self-test
Memory capacity
No. of address lines
128K ?
16M
14M

5. Introduction
For the 8086 microprocessor, there are two modes: minimum and maximum
Under different modes, the memory interface is not the same
In the minimum mode, 8086 processor is connected to the external memory block directly
In the maximum mode, a Bus controller is needed
The bus controller will issue the required control signal to drive the memory block

6. Minimum Mode ALE /BHE /RD memory /WR 8086 M/IO DT//R /DEN A16-A19
AD0-AD15

7. Address space and data organization
Memory is organized as 8-bit bytes (byte as the basic unit)
To address a word then 2 consecutive bytes are used, lower addressed byte is the LSB (Least Significant Byte) and the higher-addressed byte is the MSB (Most Significant Byte)
Words of data can be stored at even, or odd address boundaries
16-bit
MSB
LSB

8. Memory addressing
The address bit A0 of the LSB can be used to determine the address boundary. If A0 is 0 then we have an even address, or aligned
If A0 is odd then we have odd-boundary
Example: 0001H is an odd-boundary address

9. Example A0 = 1 example A0 = 0 example
A 16-bit data store at 01FFFH (then it is not aligned) and will occupy 01FFFH and 02000H (Odd boundary)
A0 = 0 example
A 16-bit data store at 02002H (then it is aligned) and will occupy 02002H and 02003H (even boundary)

10. Question
If you are asked to implement the memory system for a 8086 microprocessor, what memory configuration will you use?
One 1M Bytes chip
Two 512KBytes chips
One 1M Word chip

11. Address Space Even-boundary data can be accessed in one bus cycle
Odd-boundary word must be accessed in two bus cycle
In 8086, user’s data usually is in 8-bit or 16-bit format
For the system, instructions are always accessed as words (16-bit)
There is also double word format (32-bit)

12. Data type
Double word (32-bit) will be stored in 4 consecutive locations
When double word is used?
Double word can be used as a pointer that is used to address data or code outside the current segment
For a double word, the higher WORD stores the segment address, the lower WORD stores the offset

13. Memory organization 1M bytes memory using 2 512K byte chips
Odd boundary
Address requires
2 cycles
BHE – bank high enable

14. Hardware organization
In hardware, the 1M bytes memory is implemented as two independent 512K-byte banks
Low (even) bank, and the high (odd) bank
Data from low bank use data bus 0-7
Data from high bank use data bus 8-15
Signal A0 enables the low bank
Signal /BHE enables the high bank
/BHE is active low
How many address lines are required in order to access 512K locations? (Ans. 19)

15. Memory organization Only A1 to A19 are used to drive the memory !!!
High bank
Low bank

16. Odd-addressed word transfer
Need two cycles!
Odd address such as 1233H (low byte) H (high byte)

17. Example
Consider the 16-bit word stored at 01FFFH then it occupy 01FFFH and 02000H
In the first cycle data in 01FFFH will be read
In the second cycle data in 02000H will be read
Second case data stored in 02002H then data occupy 02002H and 02003H. Compare the bit pattern for 02002H and 02003H
02002H –
02003H –
Why both byte can be read in a single cycle?

18. Dedicated Memory locations
Dedicated memory locations should not be used
as general memory space for data and program storage
For the 8086, address to 0007F and
FFFF0 to FFFFB are dedicated
Address from FFFFC to FFFFF are reserved

19. Exercise Determine the values for A0 and /BHE in order to access
A byte at even address (/A0=0, /BHE = 1)
A byte at odd address (/A0=1, /BHE = 0)
A word at even address (aligned) (/A0=0, /BHE=0)
A word at odd address (unaligned), as shown in the
following figure
(two cycles:
First cycle get LSB /A0=1 /BHE=0
Second cycle get MSB /A0=0 /BHE =1 )

20. Memory control signals
To control the memory system in the minimum mode, requires: ALE, /BHE, M/IO, DT/R, /RD, /WR, and /DEN
ALE – address latch enable, signals external circuitry that a valid address is on the bus (0->1) so the address can be stored in the latch (or buffer)
M/IO – identify whether it is a memory or IO (Input/Output) operation (high – memory, low – I/O)
DT/R – transmit or receive (1 – transmit)
DEN – to enable the data bus

21. Read cycle of 8086 Consists of 4 time states
T1 – memory address is on the address bus, /BHE is also output, ALE is enable
Address is latch to external device at the trailing edge of ALE
T2 – M/IO and DT/R are set to 1 and 0 respectively. These signals remain their status during the cycle
Late in T2 - /RD is switched to 0 and /DEN also set to 0

22. Read cycle T3 and T4 – status bits S3, S4 are output
Data are read during T3
/RD and /DEN return to 1 at T4

23. Read Cycle

24. Write cycle
T1 – address and /BHE are output and latched with ALE pulse
M/IO is set to 1, DT/R is also set to 1
T2 - /WR set to 0 and data put on data bus
Data remain in the data bus until /WR returns to 1
When /WR returns to 1 at T4, data is written into memory

25. Write Cycle

26. Example
What is the duration of the bus cycle in the 8086-based microcomputer if the clock is 8MHz and two wait states are inserted
Ans. 750ns (6 cycles) where each clock is 125ns

27. Demultiplexing the address/data bus
Address and data must be available at the same time when data are to be transferred over the bus
Address and data must be separated using external demultiplexing circuits (eg a latch, or buffer)
Address are latched into external circuits by ALE (address latch enable ) at T1

28. Demultiplexing the system bus
One direction
Bi-direction
STB - Strobe
Latches/buffers

29. Syntax to describe a memory
Memory is usually described by its size of storage and number of data bits
Eg. A 32K bytes memory chip is represented by 32Kx8
A 32K bits memory is represented by 32Kx1

30. Configurations of memory for 16-bit data
Chip enable (CE) usually generated by some decoding mechanism
OE – output enable

31. Simple maths From 00000H to FFFFFH there are 1M memory locations
How about from 0000H to FFFFH?
How many locations between 1FFFFFH to H (answer in terms of M + K and Byte)
A memory system has 4M locations and the starting address is H what is the ending address?

32. Memory Read only memory (ROM) – nonvolatile
Data remains when power is turned off, data are written into the ROM during its fabrication at the factory
PROM- Programmable ROM. Can be programmed by user but this can only be done once
EPROM – erasable programmable ROM
Contents of EPROM can be erased by exposing it to ultraviolet light
EEPROM – Electrical Erasable PROM (your USB memory stick)

33. Exercise
There is a BIOS in your computer, what kind of memory is it?

34. Block diagram of a ROM
ROM interface – address input, data output, /CE – chip enable, /OE – output enable (for READ operation)

35. Memory Read Operation
To read a ROM, we need to issue the proper address
There is a delay between address inputs and data outputs
The access time (tACC), chip enable time (tCE), and chip deselect time (tDF) are important timing properties
You need these information for developing a real computer system

36. Timing parameters
The access time – delay occurs before data stored at the addressed location are stable at the outputs (ie how long it takes to access data). The microprocessor must wait for tACC before reading the data

37. ROM read operation
Access time is regarded as address to output delay. Typical value is 250ns
tCE – represents the Chip Enable to output delay, usually this is equal to access time
Deselect time – amount of time the device takes for data outputs to return to high-Z state after /OE becomes inactive

38. Read operation tAA=access time tCO= chip select to output delay
tHZ = deselect to output float

39. Question A normal 8086 read cycle takes 4 clocks
For a system with a 8MHz clock
Now you are required to develop the memory system for the computer which of the following devices will you use?
Tacc = 0.125us $100
Tacc = 0.2us $50
Tacc = 0.4us $20

40. Choosing the proper memory

41. Configuration of ROM for 8-bit bus
How the circuit
operates?

42. EEPROM – electrical Erasable ROM
Data stored in an EEPROM can be erased electrically
Example inside the AduC832 (or 8051) microcontroller, there are 64KBytes of EEPROM

43. Programming the EPROM In an erased EPROM, all cells hold logic 1
Vpp is in logic 1 for data to be read from EPROM
Vpp is ON (eg Vpp = 25V for 2716 EPROM) for programming mode (writing)
2716 is a 2Kx8 EPROM
To write data to the EPROM a 25V signal is needed so an external device is necessary

44. Modern EEPROM Charges in the floating gate represent the data

45. FLASH EEPROM

46. Random access memory (RAM)
Data can be read as well as written into the memory chip
Static ram (SRAM) – data remains valid as long as the power is ON
Dynamic RAM (DRAM) – needs to periodically restore (recharge) the data in each storage location by addressing them
If storage nodes are not recharged at regular intervals of time, data would be lost. This process is called refreshing

47. SRAM circuit To control RAM: CE – chip enable OE – output enable
(for read operation)
WE – write enable
(for write operation)
From
decoding
logic

48. Write-cycle for SRAM
To write, we must produce the signal in proper order
Minimum duration of a write cycle is tWC (write cycle time )
Address must remain stable during the whole cycle
Chip enable (CE) signal becomes active
The Write Enable (WE) will be active after the address setup time tAS elapses

49. RAM write operation
Data should now ready and must be valid for tDW (data valid to end of write)
Data should remain valid (tDH) after the write
A short recovery period (tWR) takes place after /WE returns to 1 before the write cycle is complete (address is removed)

50. Write cycle

51. Timing parameters for a write cycle
Time (ns)
Tc (rd) read cycle time
120
TWC (wr) write cycle time
TWP write pulse width 60
Tsu (A) address set up time 20
Tsu (S) chip select setup time
Tsu (D) data setup time 50
Th address hold time
Th (D) data hold time 5

52. Read Cycle Read cycle for RAM is similar to the ROM
Minimum duration of a read cycle is tRC (read cycle time)
Address must remain stable during the whole cycle
Chip enable becomes active
The Enable(s) (CE) will be active after the address is stable
Data should now ready
Data should remain valid after the OE and CE have been removed

53. Read Cycle CO – time between Valid data and chip enable
OE – time between
Valid data and output enable

54. DRAM DRAM has a higher density Cost less Consume less power
Take up less space
We can get 64Mx1, 128Mx1 modules

55. DRAM
An example of a DRAM – 2164B
It is a 64K-bit (64Kx1) device with only 16 pins
To address 64K address, requires 16-bit address line
16-bit address is divided into two separate parts: 8-bit row address, and 8-bit column address. And these are time-multiplexed

56. DRAM-2164B Address bus is time multiplexed RAS – row address strobe
CAS – column address strobe

57. Addressing the DRAM The row address is first applied
/RAS is pulsed to ‘0’ to latch the address into the device
The column address is applied and /CAS strobed to ‘0’
If RAS is left at ‘0’ after the row address is latched inside the device, the address is maintained within the device

58. DRAM
Data cells along the selected row can be accessed by simply supplying successive column addresses
This is called page mode accesses
(How many bits are there in a row?)
Advantage - faster access of memory is achieved

59. Addressing the DRAM-64Kx16 setup

60. Refreshing the DRAM The DRAM must be refreshed every 2ms
Refreshing is achieved by cycling through the row addresses (i.e. generating all the row address)
During refreshing, /CAS is at logic ‘1’ and no data are output

61. Example DRAM
The DRAM is 2Mx8 device and the data is parallel (8-bit) but address is multiplexed divided into ROW and Column.
In order to access 2M memory locations, it takes 21 address bits. In the device, the address lines are multiplexed into: 12 address lines for row address and column address is only 9-bit.
The refresh must be done in every 64ms.

62. DRAM

63. System memory configuration

64. Memory configuration for ADuC832

65. ADuC832 memory architecture

66. Address Decoding
Address decoding is required because many memory chips are used by a computer system
At each memory read/write only a number of chips is used
Decoding mechanism is used to guarantee that the proper chips are selected
Certainly, capacity of modern memory device is large (GB!!) so decoding may not be necessary but if you consider the development of SSD then decoding will become necessary if a SSD is 250G then you still need to use more than 1 memory device

67. Address decoding
To design, first determine the number of chips required
Then determine how many address lines are needed for the decoding purpose
Example if 4 chips are used then you need 2 address lines for decoding

68. Example
For 8086 system, max. 1M bytes of memory
Now we use 4 256Kx8 memory chip.
Note:
Even addresses memory locations should be in the same chip
Odd addresses memory locations should be in the same chip
So the 4 memory chips will be divided into Even and Odd group
(two chips per group)
Only consider the even group, since the chip is only 256K so the
Memory locations stored by one chip is from to 7FFFF (with
only the even locations)
The other chip holds to FFFFF (only the even locations)

69. Example
Odd Even
Address
80000 to FFFFF
Address
00000 to 7FFFF
Now if the address issued is 12345H which memory chip should
be selected?
What address line(s) can be used for the decoding ?

70. Decoding system Address lines used for driving the memories Memories
Decoder
Address
Used for
Selecting
The memory
block
Memories
Outputs from decoder
usually used as /CE for the memories

71. Decoder Any device that can relate its output to its inputs can be
used as a decoder
Output = f(inputs)
Inputs
Outputs
Address
Chip enable (/CE)

72. Decoding Based on the previous example
The decoding address line is A19
A19 = 0 then select addresses from 00000H – 7FFFFH
A19=1 then select addresses from 80000H – FFFFFH
A0 and BHE are used to select the even and odd
Can you identify a device that can be used for decoding?

73. Decoding Decoder /CE of 80000H – FFFFFH A19 /CE of 00000H – 7FFFFH
What is this?

74. Address Decoding Techniques
An address decoder is a circuit that examines the address lines and enables the memory (producing the /CE signals) for a specified range of addresses. This is vital in any memory design because one block of memory must not be allowed to overlap another.
Logic Gate Decoders (ANDS, ORS, NANDS, AND NORS).

75. Address Decoder circuits
A digital decoder is a circuit that recognizes a particular binary pattern on its input lines and produces an active output indication.
When will you get an active memory select?
Ans. When all inputs are 0s then the output is 0

76. NAND Gate Decoder Circuit
Output of the NAND gate is active when all inputs are 1s so
The address from A19 to A11 is (FF8)
From A0 to A10 is used to address the memory chip

77. Logic gates as decoder
A logic gate only comes with one output so if your system has many memory chips then you need one gate per memory chip!!!!!!

78. The 3-to-8 Line Decoder (74LS138)
The truth table shows that only one of the eight outputs ever goes low at any time. Three enable inputs /G2A,/G2B, and G1 must all be active.
Once the 74LS138 is enabled, the address inputs A,B, and C select which output pin goes low.
Remarks: / means logic low (0) signal level.

79. Truth Table for 74LS138 Decoder
Address
Lines will
Connect
To A, B and C

80. 64KByte Memory Bank Circuit
To enable the decoder, the NAND output (connected to G2B) must
be 0 therefore A19 to A17 must be 111. The G1 input must be 1
so A16 is 1 so address lines A19 to A16 must be 1111 (F)

81. Example-128 MB Memory Circuit

82. Example-128 MB Memory Circuit (Cont’d)
BE – Bank Enable
There are 4 banks to support data in byte, word and double word

83. How to design a decoding system
Design a memory system for a 8086 based computer
Using 64K byte memory chips.
To design the memory system, we must first identify the followings:
How many address lines for the 64Kbyte chip?
How many chips are needed for the 8086 system?
Determine the address ranges for each memory block
Determine the number of address lines can be used for decoding
Identify a suitable decoder
Draw the block diagram

84. Example How many address lines for the 64Kbyte chip? 16-bit
How many chips are needed for the 8086 system?
8086 system can address 1M so 16 chips are needed
The system should be divided into Even address and Odd address
Even address enabled by A0, Odd address enabled by BHE
8 chips will be used for the even address and a decoder can be used

85. Decoding 16 memory chips become 8 groups
Common bits
group
Address range
A19A18A17
111 7
20000H-
3FFFFH
110 6
1 0 1 5
100 4
0 11 3
0 10 2
0 0 1 1
0 0 0
00000H-
1FFFFH
16 memory chips become 8 groups
Each group includes 2 devices (even + odd)
Each group includes 128K memory locations
Assign addresses represented by each group
Look for common bit pattern within addresses of the same group
The common bits will be used for decoding

86. Self test
How many bytes can be stored by a 32Kx4 memory chip? (Ans. 16K bytes)
How many 16K bytes memory chips are required to form a 1M system? (Ans. 1M/16K = 64)
How many address lines are required to address a 16K bytes memory ? (Ans. 14)
Why the signal ALE is necessary for a 8086 microprocessor? (Ans. Because the address bus is multiplexed)
Why memory decoding is necessary for a computer system? (Ans. To select the proper memory chips when an address is issued)
What is High-block, Low-block? (High-block represents the odd memory address, low-block is the even addresses )
The two address range F8000-F8FFF and FA000-FAFFF can be decoded by what address bit(s)? (Ans. Must first examine the binary pattern of the addresses. F8000-F8FFF = (for the first two digits) FA000 – FAFFF is (for the first two digits) so the difference between the two ranges is bit A14. Therefore, A14 can be used to decode the two ranges. )

87. Exercise
Develop a 16-bit wide memory interface that contains ROM memory at locations H – 01FFFFH for the 80386SX microprocessor.
A 386SX microprocessor has 24-bit address
The ROM used is 32Kx8
The decoding logic should output signal to select the chip (/CS)
Select a proper decoding device (eg multiplexer, PAL, simple logic gates )

88. Exercise
Develop a 16-bit wide memory interface that contains SRAM memory at locations H – 21FFFFH for the 80386SX microprocessor. (total of 128K bytes)
A 386SX microprocessor has 24-bit address
The SRAM used is 32Kx8 (so you need 4 memory chips)
The decoding logic should output signal to select the chip (CS) , as well as enable the write operation (WE)
Select a proper decoding device (eg multiplexer, PAL, simple logic gates )
You can refer to Figure 10-32

89. Serial EEPROM
If building a simple device and memory is needed to store data nowadays, most commonly used memory device is serial EEPROM
As the number of pins to connect to the device is small

90. Serial EEPROM Clock and data transitions:
Data on the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will indicate a start or stop condition.
Start condition:
A high-to-low transition of SDA with SCL high is a start condition which must precede any other command
Stop condition:
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode.
Acknowledge:
The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.

91. Timing

92. Timing for data

93. Device addressing