1. CS 161 Spring 2009Course administration Instructor: Laxmi N. Bhuyan Office: 351 Engg. 2 E-mail: (bhuyan@cs.ucr.edu) Website: (http://www.ucr.edu/~bhuyan)bhuyan@cs.ucr.eduhttp://www.ucr.edu/~bhuyan Office Hours: W 3-4.00 or by appt TA:Robert Halstead E-mail: rhalstea@cs.ucr.edurhalstea@cs.ucr.edu Office Hour: Monday 4-5 pm, Tuesday 10 - 11am.

2. Course Administration Text: Computer Organization and Design: The Hardware/Software Interface, Patterson and Hennessy, 4th Ed. Prerequisite: Assembly Language (CS061) and Digital system (CS120B) Grade breakdown Test 1 (CS 61, Chapters 1 and 2) on 4-14 25% Test 2 (Chapters 2 and 4) 30% Test 3 (Chapters 5-7) 25% Homework Assignments 20% Penalty for late homework and Grades based on curve

3. Chapter 1 Computer Abstractions and Technology

4. Chapter 1 — Computer Abstractions and Technology — 4 The Computer Revolution Progress in computer technology Underpinned by Moore’s Law Makes novel applications feasible Computers in automobiles Cell phones Human genome project World Wide Web Search Engines Computers are pervasive §1.1 Introduction

5. Chapter 1 — Computer Abstractions and Technology — 5 Classes of Computers Desktop computers General purpose, variety of software Subject to cost/performance tradeoff Server computers Network based High capacity, performance, reliability Range from small servers to building sized Embedded computers Hidden as components of systems Stringent power/performance/cost constraints

6. Chapter 1 — Computer Abstractions and Technology — 6 The Processor Market

7. Chapter 1 — Computer Abstractions and Technology — 7 What You Will Learn How programs are translated into the machine language And how the hardware executes them The hardware/software interface What determines program performance And how it can be improved How hardware designers improve performance What is parallel processing

8. Chapter 1 — Computer Abstractions and Technology — 8 Understanding Performance Algorithm Determines number of operations executed Programming language, compiler, architecture Determine number of machine instructions executed per operation Processor and memory system Determine how fast instructions are executed I/O system (including OS) Determines how fast I/O operations are executed

9. Chapter 1 — Computer Abstractions and Technology — 9 Below Your Program Application software Written in high-level language System software Compiler: translates HLL code to machine code Operating System: service code Handling input/output Managing memory and storage Scheduling tasks & sharing resources Hardware Processor, memory, I/O controllers §1.2 Below Your Program

10. What is “Computer Architecture”? I/O systemProcessor Compiler Operating System (Unix; Windows 9x) Application (Netscape) Digital Design Circuit Design Instruction Set Architecture Key Idea: levels of abstraction hide unnecessary implementation details helps us cope with enormous complexity of real systems Datapath & Control transistors, IC layout Memory Hardware Software Assembler CS 161

11. The Instruction Set: A Critical Interface instruction set software hardware

12. Chapter 1 — Computer Abstractions and Technology — 12 Levels of Program Code High-level language Level of abstraction closer to problem domain Provides for productivity and portability Assembly language Textual representation of instructions Hardware representation Binary digits (bits) Encoded instructions and data

13. Chapter 1 — Computer Abstractions and Technology — 13 Components of a Computer Same components for all kinds of computer Desktop, server, embedded Input/output includes User-interface devices Display, keyboard, mouse Storage devices Hard disk, CD/DVD, flash Network adapters For communicating with other computers §1.3 Under the Covers The BIG Picture

14. Chapter 1 — Computer Abstractions and Technology — 14 Anatomy of a Computer Output device Input device Network cable

15. Chapter 1 — Computer Abstractions and Technology — 15 Inside the Processor AMD Barcelona: 4 processor cores

16. Chapter 1 — Computer Abstractions and Technology — 16 A Safe Place for Data Volatile main memory Loses instructions and data when power off Non-volatile secondary memory Magnetic disk Flash memory Optical disk (CDROM, DVD)

17. Chapter 1 — Computer Abstractions and Technology — 17 Networks Communication and resource sharing Local area network (LAN): Ethernet Within a building Wide area network (WAN: the Internet Wireless network: WiFi, Bluetooth

18. The von Neumann Computer Stored-Program Concept – Storing programs as numbers – by John von Neumann – Eckert and Mauchly worked in engineering the concept. Idea: A program is written as a sequence of instructions, represented by binary numbers. The instructions are stored in the memory just as data. They are read one by one, decoded and then executed by the CPU.

19. Historical Perspective 1944: The First Electronic Computer ENIAC at IAS, Princeton Univ. (18,000 vacuum tubes) Decade of 70’s (Microprocessors) Programmable Controllers, Single Chip Microprocessors Personal Computers Decade of 80’s (RISC Architecture) Instruction Pipelining, Fast Cache Memories Compiler Optimizations Decade of 90’s (Instruction Level Parallelism) Superscalar Processors, Instruction Level Parallelism (ILP), Aggressive Code Scheduling, Out of Order Execution Decade of 2000’s (Multi-core processors) Thread Level Parallelism (TLP), Low Cost Supercomputing

20. Performance Growth In Perspective Doubling every 18 months since 1982 Cars travel at 11,000 mph; get 4000 miles/gal Air Travel LA-NY in 90 seconds (Mach 200) Wheat yield 20,000 bushels per acre Doubling every 24 months since 1970 Cars travel at 200,000 mph; get 50,000 miles/gal Air Travel LA-NY in 6 seconds (Mach 3,000) Wheat yield 300,000 bushels per acre

21. Technology => Dramatic Change Processor 2X in performance every 1.5 years; 1000X performance in last decade (Moore’s Law) Main Memory DRAM capacity: 2x / 2 years; 1000X size in last decade Cost/bit: improves about 25% per year Disk capacity: > 2X in size every 1.5 years Cost/bit: improves about 60% per year

22. Chapter 1 — Computer Abstractions and Technology — 22 Technology Trends Electronics technology continues to evolve Increased capacity and performance Reduced cost YearTechnologyRelative performance/cost 1951Vacuum tube1 1965Transistor35 1975Integrated circuit (IC)900 1995Very large scale IC (VLSI)2,400,000 2005Ultra large scale IC6,200,000,000 DRAM capacity

23. Chapter 1 — Computer Abstractions and Technology — 23 Manufacturing ICs Yield: proportion of working dies per wafer §1.7 Real Stuff: The AMD Opteron X4

24. Chapter 1 — Computer Abstractions and Technology — 24 AMD Opteron X2 Wafer X2: 300mm wafer, 117 chips, 90nm technology X4: 45nm technology

25. Chapter 1 — Computer Abstractions and Technology — 25 Integrated Circuit Cost Nonlinear relation to area and defect rate Wafer cost and area are fixed Defect rate determined by manufacturing process Die area determined by architecture and circuit design

26. Chapter 1 — Computer Abstractions and Technology — 26 Defining Performance Which airplane has the best performance? §1.4 Performance

27. Chapter 1 — Computer Abstractions and Technology — 27 Response Time and Throughput Response time How long it takes to do a task Throughput Total work done per unit time e.g., tasks/transactions/… per hour How are response time and throughput affected by Replacing the processor with a faster version? Adding more processors? We’ll focus on response time for now…

28. Chapter 1 — Computer Abstractions and Technology — 28 Relative Performance Define Performance = 1/Execution Time “X is n time faster than Y” Example: time taken to run a program 10s on A, 15s on B Execution Time B / Execution Time A = 15s / 10s = 1.5 So A is 1.5 times faster than B

29. Chapter 1 — Computer Abstractions and Technology — 29 Measuring Execution Time Elapsed time Total response time, including all aspects Processing, I/O, OS overhead, idle time Determines system performance CPU time Time spent processing a given job Discounts I/O time, other jobs’ shares Comprises user CPU time and system CPU time Different programs are affected differently by CPU and system performance

30. Chapter 1 — Computer Abstractions and Technology — 30 CPU Clocking Operation of digital hardware governed by a constant-rate clock Clock (cycles) Data transfer and computation Update state Clock period Clock period: duration of a clock cycle e.g., 250ps = 0.25ns = 250×10 –12 s Clock frequency (rate): cycles per second e.g., 4.0GHz = 4000MHz = 4.0×10 9 Hz

31. Chapter 1 — Computer Abstractions and Technology — 31 CPU Time Performance improved by Reducing number of clock cycles (good algorithm or hardware design) Increasing clock rate (good technology) Hardware designer must often trade off clock rate against cycle count

32. Chapter 1 — Computer Abstractions and Technology — 32 CPU Time Example Computer A: 2GHz clock, 10s CPU time Designing Computer B Aim for 6s CPU time Can do faster clock, but causes 1.2 × clock cycles How fast must Computer B clock be?

33. Chapter 1 — Computer Abstractions and Technology — 33 Instruction Count and CPI Instruction Count for a program Determined by program, ISA and compiler Average cycles per instruction Determined by CPU hardware If different instructions have different CPI Average CPI affected by instruction mix

34. Chapter 1 — Computer Abstractions and Technology — 34 CPI Example Computer A: Cycle Time = 250ps, CPI = 2.0 Computer B: Cycle Time = 500ps, CPI = 1.2 Same ISA Which is faster, and by how much? A is faster… …by this much

35. Chapter 1 — Computer Abstractions and Technology — 35 CPI in More Detail If different instruction classes take different numbers of cycles Weighted average CPI Relative frequency

36. Chapter 1 — Computer Abstractions and Technology — 36 CPI Example Alternative compiled code sequences using instructions in classes A, B, C ClassABC CPI for class123 IC in sequence 1212 IC in sequence 2411 Sequence 1: IC = 5 Clock Cycles = 2×1 + 1×2 + 2×3 = 10 Avg. CPI = 10/5 = 2.0 Sequence 2: IC = 6 Clock Cycles = 4×1 + 1×2 + 1×3 = 9 Avg. CPI = 9/6 = 1.5

37. Chapter 1 — Computer Abstractions and Technology — 37 Performance Summary Performance depends on Algorithm: affects IC, possibly CPI Programming language: affects IC, CPI Compiler: affects IC, CPI Instruction set architecture: affects IC, CPI, T c The BIG Picture

38. Chapter 1 — Computer Abstractions and Technology — 38 Power Trends In CMOS IC technology §1.5 The Power Wall ×1000 ×30 5V → 1V

39. Chapter 1 — Computer Abstractions and Technology — 39 Reducing Power Suppose a new CPU has 85% of capacitive load of old CPU 15% voltage and 15% frequency reduction The power wall We can’t reduce voltage further We can’t remove more heat How else can we improve performance?

40. Chapter 1 — Computer Abstractions and Technology — 40 Uniprocessor Performance §1.6 The Sea Change: The Switch to Multiprocessors Constrained by power, instruction-level parallelism, memory latency

41. Chapter 1 — Computer Abstractions and Technology — 41 Multiprocessors Multicore microprocessors More than one processor per chip Requires explicitly parallel programming Compare with instruction level parallelism Hardware executes multiple instructions at once Hidden from the programmer Hard to do Programming for performance Load balancing Optimizing communication and synchronization

42. Chapter 1 — Computer Abstractions and Technology — 42 SPEC CPU Benchmark Programs used to measure performance Supposedly typical of actual workload Standard Performance Evaluation Corp (SPEC) Develops benchmarks for CPU, I/O, Web, … SPEC CPU2006 Elapsed time to execute a selection of programs Negligible I/O, so focuses on CPU performance Normalize relative to reference machine Summarize as geometric mean of performance ratios CINT2006 (integer) and CFP2006 (floating-point)

43. Chapter 1 — Computer Abstractions and Technology — 43 CINT2006 for Opteron X4 2356 NameDescriptionIC×10 9 CPITc (ns)Exec timeRef timeSPECratio perlInterpreted string processing2,1180.750.406379,77715.3 bzip2Block-sorting compression2,3890.850.408179,65011.8 gccGNU C Compiler1,0501.720.47248,05011.1 mcfCombinatorial optimization33610.000.401,3459,1206.8 goGo game (AI)1,6581.090.4072110,49014.6 hmmerSearch gene sequence2,7830.800.408909,33010.5 sjengChess game (AI)2,1760.960.483712,10014.5 libquantumQuantum computer simulation1,6231.610.401,04720,72019.8 h264avcVideo compression3,1020.800.4099322,13022.3 omnetppDiscrete event simulation5872.940.406906,2509.1 astarGames/path finding1,0821.790.407737,0209.1 xalancbmkXML parsing1,0582.700.401,1436,9006.0 Geometric mean11.7 High cache miss rates

44. Chapter 1 — Computer Abstractions and Technology — 44 SPEC Power Benchmark Power consumption of server at different workload levels Performance: ssj_ops/sec Power: Watts (Joules/sec)

45. Chapter 1 — Computer Abstractions and Technology — 45 SPECpower_ssj2008 for X4 Target Load %Performance (ssj_ops/sec)Average Power (Watts) 100%231,867295 90%211,282286 80%185,803275 70%163,427265 60%140,160256 50%118,324246 40%920,35233 30%70,500222 20%47,126206 10%23,066180 0%0141 Overall sum1,283,5902,605 ∑ssj_ops/ ∑power493

46. Chapter 1 — Computer Abstractions and Technology — 46 Pitfall: Amdahl’s Law Improving an aspect of a computer and expecting a proportional improvement in overall performance §1.8 Fallacies and Pitfalls Can’t be done! Example: multiply accounts for 80s/100s How much improvement in multiply performance to get 5× overall? Corollary: make the common case fast

47. Chapter 1 — Computer Abstractions and Technology — 47 Fallacy: Low Power at Idle Look back at X4 power benchmark At 100% load: 295W At 50% load: 246W (83%) At 10% load: 180W (61%) Google data center Mostly operates at 10% – 50% load At 100% load less than 1% of the time Consider designing processors to make power proportional to load

48. Chapter 1 — Computer Abstractions and Technology — 48 Pitfall: MIPS as a Performance Metric MIPS: Millions of Instructions Per Second Doesn’t account for Differences in ISAs between computers Differences in complexity between instructions CPI varies between programs on a given CPU

49. Chapter 1 — Computer Abstractions and Technology — 49 Concluding Remarks Cost/performance is improving Due to underlying technology development Hierarchical layers of abstraction In both hardware and software Instruction set architecture The hardware/software interface Execution time: the best performance measure Power is a limiting factor Use parallelism to improve performance §1.9 Concluding Remarks