1. Topic 4: Digital Circuits
(Integrated Circuits Technology)

2. What is on the agenda? Introduction
Basic Operational Characteristics and Parameters of Integrated Circuits
CMOS Technology
Bipolar Technology
Some Practical considerations

3. 1. Introduction
So far we have analyzed the mathematical theory (combinational logic fundamentals) that presents some of the logic concepts commonly used in digital systems design.
We will be more concerned here about technology. It can be defined as means and physical implementations of real digital circuits whose behaviors are dictated by the digital laws previously studied.
To understand some of the issues related to the technology, a number of questions must be answered such as:
What type electronic basic element (passive or active) can be used to implement a simple logic gate such as an “inverter”?
How efficiently is an implementation in terms of power and speed?
What is the level of integration?
How to characterize a digital electronic device?
We are very fortunate that these questions were answered properly in the past by many physicists. We will present here their outcomes in terms of technology.

4. 2. Basic Operational Characteristics and parameters
Digital components are called “Integrated circuits”. They are implemented using transistors.
In Digital electronics, transistors are always configured to work in switching modes.
The type of transistor being used defines the technology:
TTL (transistor-transistor-logic) for bipolar transistors
CMOS (complementary MOS) for MOSFET transistors.
MOSFET = metal-oxide semiconductor field-effect transistor
The following figure show an IC packages that contains “nand” gates.

5. Figure 1: IC Package containing Nand Gates.

6. 2.1. Logic Levels
The concept of logic levels is used to represent logic variables in digital electronic circuits.
There are four different logic-level specifications:
VIL (Voltage input Low)
VIH (Voltage input high)
VOL (Voltage output low)
VOH (Voltage output high)
Figures 2 and 3 show the CMOS and TTL logic Levels respectively.

7. Figure 2: Inputs and output logic levels for CMOS

8. Figure 3: Input and output Logic levels for TTL
Figures 2 and 3 show clearly that these two technology don’t support all the ranges of voltages. If and input falls into the unallowed region the behavior of the circuit is unpredicatble, therefore its output doesn’t represent a valuable information

9. 2.2. Noise
Noise is unwanted voltage that is included in electrical circuits and can present a threat to a proper operation of the circuit.
Examples of noise:
Thermal noise
Electromagnetic noise
Power-line voltage fluctuation noise
In order not to be adversely affected by noise, a logic circuit must have a certain amount of noise immunity.
The following figure shows some of the consequences of noise on a logic gate.

10. Noise – unwanted variations of voltages and currents at the logic nodes
from two wires placed side by side
capacitive coupling
voltage change on one wire can influence signal on the neighboring wire
cross talk
inductive coupling
current change on one wire can influence signal on the neighboring wire
v(t)
i(t)
VDD
from noise on the power and ground supply rails
can influence signal levels in the gate

11. Large noise margins are desirable, but not sufficient …
For robust circuits, want the “0” and “1” intervals to be a s large as possible
VDD
VDD
VOHmin
"1"
NMH = VOHmin - VIHmin
NML = VILmax - VOLmax
VIHmin
Noise Margin High
Noise Margin Low
Undefined
Region
VILmax
VOLmax
model is Gate Output of inverter1 feeding Gate Input of inverter2
Noise margin represents the levels of noise that can be sustained when gates are cascaded – obviously noise margins should be as large as possible
"0"
Gnd
Gnd
Gate Output
Gate Input
Large noise margins are desirable, but not sufficient …

12. 2.3 Noise Immunity
Noise margin expresses the ability of a circuit to overpower a noise source
noise sources: supply noise, cross talk, interference, offset
Absolute noise margin values are deceptive
a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage)
Noise immunity expresses the ability of the system to process and transmit information correctly in the presence of noise
For good noise immunity, the signal swing (i.e., the difference between VOH and VOL) and the noise margin have to be large enough to overpower the impact of fixed sources of noise
IMPEDANCE – (not inductance!!)
Want output impedance of the driver to be zero ideally
Input impedance of the receiver to be infinity ideally
The two together give unlimited fanout

13. 2.4 Static Gate Behavior
Steady-state parameters of a gate – static behavior – tell how robust a circuit is with respect to both variations in the manufacturing process and to noise disturbances.
Digital circuits perform operations on Boolean variables x {0,1}
A logical variable is associated with a nominal voltage level for each logic state
1  VOH and 0  VOL
! = complement
V(y)
V(x)
VOH = ! (VOL)
VOL = ! (VOH)
Difference between VOH and VOL is the logic or signal swing Vsw

14. 2.5 DC Operation Voltage Transfer Characteristics (VTC)
Plot of output voltage as a function of the input voltage
V(y)
V(x)
V(y) f
VOH = f (VIL)
V(y)=V(x)
Switching Threshold VM
VM is the intersection of the VTC curve and the line given by Vout = Vin
VOL = f (VIH)
VIL
VIH
V(x)

15. 2.6. Mapping Logic Levels to the Voltage Domain
The regions of acceptable high and low voltages are delimited by VIH and VIL that represent the points on the VTC curve where the gain = -1
"1"
"0"
Undefined
Region
VOH
VOL
VIL
VIH
V(y)
Slope = -1
VOH
Slope = -1 are unity gain points
Slope = -1
VOL
VIL
VIH
V(x)

16. 2.7 Directivity
A gate must be undirectional: changes in an output level should not appear at any unchanging input of the same circuit
In real circuits full directivity is an illusion (e.g., due to capacitive coupling between inputs and outputs)
Key metrics: output impedance of the driver and input impedance of the receiver
ideally, the output impedance of the driver should be zero
input impedance of the receiver should be infinity
IMPEDANCE – (not inductance!!)
Want output impedance of the driver to be zero ideally
Input impedance of the receiver to be infinity ideally
The two together give unlimited fanout

17. 2.8 Fan-In and Fan-Out
Fan-out – number of load gates connected to the output of the driving gate
gates with large fan-out are slower N M
Fan-in – the number of inputs to the gate
gates with large fan-in are bigger and slower

18. 2.9 The Ideal Inverter The ideal gate should have
infinite gain in the transition region
a gate threshold located in the middle of the logic swing
high and low noise margins equal to half the swing
input and output impedances of infinity and zero, resp.
Vout
Ri = 
Ro = 0
Fanout = 
NMH = NML = VDD/2
g = - 
For lecture
Vin

19. 2.10 Delay Definitions Vin Vout Vin t Vout t Propagation delay? input
waveform t
Vout
For class handout
output
waveform
signal slopes? t

20. Delay Definitions Vin Vout Vin tp = (tpHL + tpLH)/2 tpHL tpLH t Vout
Propagation delay
input
waveform
50%
tpHL
tpLH t
Vout
For lecture
Delay is a function of fan-in and fan-out (increases load)
90%
10% tr tf
output
waveform
signal slopes t

21. 2.10 Modeling Propagation Delay
Model circuit as first-order RC network
vout (t) = (1 – e–t/)V
where  = RC R
vout C
Time to reach 50% point is
t = ln(2)  = 0.69 
vin
Of interest is the propagation delay.
When applying a step input (with vin going from 0 to V), the transient response of this circuit is known to be an exponential function (tau = RC, the time constant of the network)
Time to reach 90% point is
t = ln(9)  = 2.2 
Matches the delay of an inverter gate

22. 2.11 Power and Energy Dissipation
Power consumption: how much energy is consumed per operation and how much heat the circuit dissipates
supply line sizing (determined by peak power)
Ppeak = Vddipeak
battery lifetime (determined by average power dissipation)
p(t) = v(t)i(t) = Vddi(t) Pavg= 1/T  p(t) dt = Vdd/T  idd(t) dt
packaging and cooling requirements
Two important components: static and dynamic

23. Propagation delay and the power consumption of a gate are related
Propagation delay is (mostly) determined by the speed at which a given amount of energy can be stored on the gate capacitors
the faster the energy transfer (higher power dissipation) the faster the gate
For a given technology and gate topology, the product of the power consumption and the propagation delay is a constant
Power-delay product (PDP) – energy consumed by the gate per switching event
An ideal gate is one that is fast and consumes little energy, so the ultimate quality metric is
Energy-delay product (EDP) = power-delay 2

24. 3. CMOS Technology
The basic building blocks in CMOS logic circuits are MOS transistors.

25. 3.1 MOS Transistors

26. NMOS transistor Gate Source Drain Substrate (Body) (a) NMOS transistorV G V V S D
(b) Simplified symbol for an NMOS transistor
NMOS transistor

27. PMOS transistor Gate Drain Source V Substrate (Body)DD
Substrate (Body)
(a) PMOS transistor V G V V S D
(b) Simplified symbol for an PMOS transistor
PMOS transistor

34. A NOT gate built using NMOS technologyV DD R R +
5 V - V V f f V V x x
(a) Circuit diagram
(b) Simplified circuit diagram x f x f
(c) Graphical symbols
A NOT gate built using NMOS technology

35. NMOS realization of a NAND gateV DD V f V x 1 x x f 1 2 1 V x 2 1 1 1 1 1 1
(a) Circuit
(b) Truth table x x 1 1 f f x x 2 2
(c) Graphical symbols
NMOS realization of a NAND gate

36. NMOS realization of a NOR gate

37. Figure 3.8 NMOS realization of an AND gateV V DD DD V f A V x 1 x x f 1 2 V x 2 1 1 1 1 1
(a) Circuit
(b) Truth table x x 1 1 f f x x 2 2
(c) Graphical symbols
Figure NMOS realization of an AND gate

38. NMOS realization of an OR gate