1. Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ CprE 281: Digital Logic

2. T Flip-Flops CprE 281: Digital Logic Iowa State University, Ames, IA Copyright © Alexander Stoytchev

3. Administrative Stuff The FINAL exam is scheduled for Wednesday Dec. 18 @ 7:30-9:30 AM That is 7:30 AM  It will be in this room.

4. Administrative Stuff Midterm 2 is now graded Check your grade on Blackboard Sample solutions are posted on the class web page The exams will be returned today after class. If your lab was on Tuesday or this morning, then you should have gotten your exam back from your TAs during the lab.

5. Quick Review

6. Edge-Triggered D Flip-Flops

7. Motivation In some cases we need to use a memory storage device that can change its state no more than once during each clock cycle.

8. (a) Circuit D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk [ Figure 5.9a from the textbook ] Master-Slave D Flip-Flop

9. D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk [ Figure 5.9a,b from the textbook ] Timing Diagram for the Master-Slave D Flip-Flop D Clock Q m QQ s =

10. D Q Q [ Figure 5.9c from the textbook ] Graphical Symbol for the Master-Slave D Flip-Flop

11. D Q Q [ Figure 5.9c from the textbook ] Graphical Symbol for the Master-Slave D Flip-Flop The > means that this is edge-triggered The small circle means that is is the negative edge

12. D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk Negative-Edge-Triggered Master-Slave D Flip-Flop Positive-Edge-Triggered Master-Slave D Flip-Flop D Q Q MasterSlave D Clock Q Q D Q Q Q m Q s Clk

13. Negative-Edge-Triggered Master-Slave D Flip-Flop Positive-Edge-Triggered Master-Slave D Flip-Flop D Q Q D Q Q

14. Other Types of Edge-Triggered D Flip-Flops

15. D Clock Q a Q b Q c D Q Q D Q Q D Q Q D Q a Q b Q c Q c Q b Q a Clk Comparison of level-sensitive and edge-triggered D storage elements

16. D Clock Q a Q b Q c D Q Q D Q Q D Q Q D Q a Q b Q c Q c Q b Q a Clk Comparison of level-sensitive and edge-triggered D storage elements Level-sensitive (the output mirrors the D input when Clk=1)

17. D Clock Q a Q b Q c D Q Q D Q Q D Q Q D Q a Q b Q c Q c Q b Q a Clk Comparison of level-sensitive and edge-triggered D storage elements Positive-edge-triggered

18. D Clock Q a Q b Q c D Q Q D Q Q D Q Q D Q a Q b Q c Q c Q b Q a Clk Comparison of level-sensitive and edge-triggered D storage elements Negative-edge-triggered

19. D Clock P4 P3 P1 P2 5 6 1 2 3 (a) Circuit D Q Q (b) Graphical symbol Clock Q Q 4 [ Figure 5.11 from the textbook ] A positive-edge-triggered D flip-flop

20. D Clock P4 P3 P1 P2 5 6 1 2 3 (a) Circuit D Q Q (b) Graphical symbol Clock Q Q 4 [ Figure 5.11 from the textbook ] A positive-edge-triggered D flip-flop This circuit behaves like a positive-edge-triggered D flip-flop, but it uses only 6 NAND gates. Thus, it can be implemented with fewer transistors than the master-slave D flip-flop.

21. [ Figure 5.12 from the textbook ] Master-slave D flip-flop with Clear and Preset

22. Positive-edge-triggered D flip-flop with Clear and Preset

23. [ Figure 5.13a from the textbook ] Positive-edge-triggered D flip-flop with Clear and Preset

24. [ Figure 5.13b,c from the textbook ] Positive-edge-triggered D flip-flop with Clear and Preset

25. [ Figure 5.14 from the textbook ] Flip-Flop Timing Parameters

26. T Flip-Flop

27. Motivation A slight modification of the D flip-flop that can be used for some nice applications.

28. [ Figure 5.15a from the textbook ] T Flip-Flop

29. [ Figure 5.15a from the textbook ] T Flip-Flop Positive-edge-triggered D Flip-Flop

30. [ Figure 5.15a from the textbook ] T Flip-Flop What is this?

31. Q Q T D

32. Q Q T D += ?

33. T 0 1 D Q Q Clock T Flip-Flop

34. T Flip-Flop (How it Works) If T=0 then it stays in its current state If T=1 then it reverses its current state In other words the circuit “toggles” its state when T=1. This is why it is called T flip-flop.

35. [ Figure 5.15a,b from the textbook ] T Flip-Flop (circuit and truth table)

36. [ Figure 5.15a,c from the textbook ] T Flip-Flop (circuit and graphical symbol)

37. [ Figure 5.15d from the textbook ] T Flip-Flop (Timing Diagram)

38. Questions?

39. THE END