1. Sequential Networks Two major classes of Sequential Circuits 1.Fundamental Mode – A sequential circuit where: Only one input is allowed to change at any given time no input change is permitted until internal changes caused by previous input transition have completed. (stable input transition property) Example: latches and flip-flops 2. Pulse Mode – A sequential circuit that responds only to pulses Example: clocked synchronous systems

2. Model of Sequential Networks Combinational Logic Circuit Memory Elements - flip-flop - latch - register - PROM n m ss s-bit Present State Variables, Y s-bit Next State Excitation Variables E i (X,Y) Input Variables, X Output Variable, Z y i (t+  t i ) x i (t) y i (t)

3. Sequential Logic Model Composed of Combinational Logic and Memory Elements Behavior is Given by Logic values at Discrete Time Instances Discrete Time Instances are Given by Clock Signal Memory Elements –Edge-Triggered Flip-Flops –Level-Sensitive Latches Memory Elements Can Only Load at Discrete Time Instance

4. Signal Signal Review time voltage f = 1/  PwPw rising edge falling edge  - clock period (in Seconds) P w - pulse width (in Seconds) f – clock frequency (in Hertz) duty cycle - ratio of pulse width to period (in %) duty cycle = P w /  

5. Clock Signal Example What is the pulse-width of a 4.77 MHz clock with a 30% duty cycle?  = 1/f = (4.77×10 6 ) -1 = 2.096 ×10 -7 = 210 ns P w = (duty cycle) ×  = (0.3) × (210 ns) = 63 ns What about clock rise- and fall-time? Clocks are normally defined as having maximum rise and fall times (e.g., time between 10% and 90% values) or they are implied through pulse width specifications.

6. Common Memory Element - Flip-Flops S R Q Q Q Q J K Q Q DQ Q T Behavior is Described by Characteristic Table or Equation Most Commonly Encountered Device is the D-flip-flop

7. Concept of State The Q Outputs of the Flip-Flops Form a State Vector A Particular Set of Outputs is the Present State The Particular State Vector that will Occur at the Next Discrete Time is the Next State A Sequential Circuit described in Terms of State is a Finite State Machine (FSM)

8. FSM Analysis Example x CLK A B y State Equations: Preset State: A (t)B (t) Next State: A(t+1)B(t+1)

9. Representing/Describing FSMs 00 0111 0/0 0/1 1/0 0/1 1/0 Present State Output Input Transition Table State Diagram 10 Note a State Table does not necessarily have the state assignment

10. Representing/Describing FSMs State Table Timing Diagram CLK A B x y Note: propagation delays and change in y before clock edge

11. FSM Design Specification Given as One of Previous Descriptions –State Table –State Equations –State Diagram(Easiest to Generate Initially) –ASM Chart(Preferred) Designer’s Job is to Generate Schematic Instead of Characteristics, we are Given Excitations Individual flip-flops have Specific Excitations

12. Flip-Flop Excitations S R Q Q Q Q J K Q Q DQ Q T Input Behavior is Described by Excitation Table or Equation Most Commonly Encountered Device is the D-flip-flop

13. Alternate Scheme for Mapping Excitation for SR Latch in One Map S, R, s, and r cannot be 1 at the same time, one map can be used for generating Set and Reset equations For Set must encircle S and s is don’t care For Reset must encircle R and r is don’t care

14. Vending Machine Example (US version) Soft drink sells for $.75 Machine accepts quarter and half-dollar coins Input x 1 =1 if machine receives a half-dollar Input x 2 = 1 if machine receives a quarter Output z 1 = 1 if machine is to give drink Output z 2 = 1 if machine is to give change

15. Vending Machine Example State Diagram and State Table Q 0, initial state without money Q 2, machine received a half-dollar Q 1, machine received a quarter

16. Vending Machine Example State Assignment and Transition Table

17. Vending Machine Example SR Implementation with Separate Maps

18. Vending Machine Example SR Implementation with Single Maps r 00011110 00 01 11 10 y 1 y 2 x 1 x 2 s r r r S dd d d d d d S RR y1y1 r 00011110 00 01 11 10 y 1 y 2 x 1 x 2 r s S R r dd d d d d d R rr y2y2

19. Vending Machine Example Outputs 00011110 00 01 11 10 y 1 y 2 x 1 x 2 1 dd d d d d d11 z1z1 00011110 00 01 11 10 y 1 y 2 x 1 x 2 dd d d d d d1 z2z2