1. SEQUENTIAL CIRCUITS Introduction1

2. Overview Circuits require memory to store intermediate data
Sequential circuits use a periodic signal to determine when to store values.
A clock signal can determine storage times
Clock signals are periodic
Single bit storage element is a flip flop
A basic type of flip flop is a latch
Latches are made from logic gates
NAND, NOR, AND, OR, Inverter
credential:
bring a computer
die photo
wafer :
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

3. The story so far ...
Logical operations which respond to combinations of inputs to produce an output.
Call these combinational logic circuits.
Usually these circuits do not contain loops
However, some combinational circuits have loops: 3

4. The story so far ... Combinational circuits
No way of remembering or storing information after inputs have been removed.
To handle this, we need sequential logic capable of storing intermediate (and final) results. 4

5. Sequential Circuits a periodic external event (input) Inputs
Combinational circuit
Flip Flops
Outputs
Inputs
Next state
Present state
Timing signal (clock)
Clock
a periodic external event (input)
synchronizes when current state changes happen
keeps system well-behaved
makes it easier to design and build large systems

6. Cross-coupled Inverters
The system has two stable states
A stable value can be stored at inverter outputs
Not possible to set a desired state
State 2
State 1 6

7. Cross-coupled Inverters (cont.)
This circuit has no stable states 7

8. S-R Latch with NORs S-R latch made from cross-coupled NORs
R (reset) Q
S R Q Q’
0 0 Forbidden
1 1
1 0
0 1
0 0
1 0 Set
0 1 Reset Q
0 1
Stable
S (set)
1 0
S-R latch made from cross-coupled NORs
If Q = 1, set state
If Q = 0, reset state
Usually S=0 and R=0
S=1 and R=1 generates unpredictable results
reset
set S R Q 8

9. S-R Latch with NORs R (reset) Q Q S (set) S R Q Q’ 0 0 Forbidden 1 1
1 1
1 0
0 1
0 0
1 0 Set
0 1 Reset Q
0 1
Stable
S (set)
1 0 9

10. S-R Latch with NORs
R (reset) Q
S R Q Q’
0 0 Forbidden
1 1
1 0
0 1
0 0
1 0 Set
0 1 Reset Q
0 1
Stable
S (set)
1 0
What happens if both inputs R and S simultaneously change from 0 to 1?
Race conditions 10

11. S-R Latch with NANDs S Q Q’ R S R Q Q’ 0 0 1 1 Forbidden 0 1 1 0 1 1
0 0
0 1
1 0
1 1
1 1 Forbidden
1 0 Set
0 1 Reset
0 1
Store
1 0
Latch made from cross-coupled NANDs
Sometimes called S’-R’ latch
Usually S=1 and R=1
S=0 and R=0 generates unpredictable results

12. S-R Latches 12

13. NOR S-R Latch with Control Input
Latch is level-sensitive, in regards to C
Only stores data if C’ = 0 R’ Q C’ Q’
Latch operation enabled by C S’
Outputs change when C is low:
RESET and SET
Otherwise: HOLD
Input sampling enabled by gates 13

14. S-R Latch with control input
Occasionally, desirable to avoid latch changes
C = 0 disables all latch state changes
Control signal enables data change when C = 1
Right side of circuit same as ordinary S-R latch. 14

15. D Latch
Q0 indicates the previous state (the previously stored value) X S D Q C Q’ R Y
X Y C Q Q’
Q0 Q0’ Store
Reset
Set
Disallowed
X X 0 Q0 Q0’ Store
X 0 Q0 Q0’
D C Q Q’

16. D Latch D Q C Q’ X S R Y D C Q Q’ 0 1 0 1 1 1 1 0 X 0 Q0 Q0’
X 0 Q0 Q0’
D C Q Q’
Input value D is passed to output Q when C is high
Input value D is ignored when C is low

17. D Latch D Q C E E Latches on following edge of clock x z x
Z only changes when E is high
If E is high, Z will follow X z

18. D Latch D Q C E E Latches on following edge of clock x x z z
The D latch stores data indefinitely, regardless of input D values, if C = 0
Forms basic storage element in computers

19. Enabling Signal E D Q C x z
Complete the waveform

20. E D Q C x z
Complete the waveform

21. Symbols for Latches SR latch is based on NOR gates
S’R’ latch based on NAND gates
D latch can be based on either.
D latch sometimes called transparent latch 21

22. Notes Latches are based on combinational gates (e.g. NAND, NOR)
Latches store data even after data input has been removed
S-R latches operate like cross-coupled inverters with control inputs (S = set, R = reset)
With additional gates, an S-R latch can be converted to a D latch (D stands for data)
D latch is simple to understand conceptually
When C = 1, data input D stored in latch and output as Q
When C = 0, data input D ignored and previous latch value output at Q
Next time: more storage elements!

23. Why FFs Latches respond to trigger levels on control inputs
Example: If G = 1, input reflected at output
Difficult to precisely time when to store data with latches
Flip flips store data on a rising or falling trigger edge.
Example: control input transitions from 0 -> 1, data input appears at output
Data remains stable in the flip flop until until next rising edge.
Different types of flip flops serve different functions
Flip flops can be defined with characteristic functions.

24. Disadvantage of Transparent Latches
Difficult to implement a shift register! 24

25. Clocking Event C D Q Q’ Lo-Hi edge Hi-Lo edge
What if the output only changed on a C transition? C D Q Q’
X 0 Q0 Q0’
D C Q Q’
Positive edge triggered
Lo-Hi edge
Hi-Lo edge

26. Master-Slave D Flip Flop
Consider two latches combined together
Only one C value active at a time
Output changes on falling edge of the clock
D C Q Q’
X 0 Q0 Q0’ 26

27. D Flip-Flop C D Q Q’ Stores a value on the positive edge of C
Input changes at other times have no effect on output C D Q Q’
X 0 Q0 Q0’
D C Q Q’
Positive edge triggered
D gets latched to Q on the rising edge of the clock.

28. Clocked D Flip-Flop Stores a value on the positive edge of C
Input changes at other times have no effect on output 28

29. Positive and Negative Edge D Flip-Flop
D flops can be triggered on positive or negative edge
Bubble before Clock (C) input indicates negative edge trigger
Lo-Hi edge
Hi-Lo edge

30. Positive Edge-Triggered J-K Flip-Flop
CLK Q Q’
Created from D flop
J sets
K resets
J=K=1 -> invert output
0 0
Q0 Q0’
0 1
1 0
1 1
TOGGLE 30

31. Clocked J-K Flip Flop Two data inputs, J and K
J -> set, K -> reset, if J=K=1 then toggle output
Characteristic Table 31

32. Positive Edge-Triggered T Flip-Flop
Created from D flop
T=0 -> keep current
K resets
T=1 -> invert current
Q0 Q0’ 1
TOGGLE Q Q’ C T

33. J, K are synchronous inputs
Asynchronous Inputs
J, K are synchronous inputs
Effects on the output are synchronized with the CLK input.
Asynchronous inputs operate independently of the synchronous inputs and clock
Set the FF to 1/0 states at any time. 33

34. Asynchronous Inputs 34

35. Asynchronous Inputs Note reset signal (R) for D flip flop
If R = 0, the output Q is cleared
This event can occur at any time, regardless of the value of the CLK 35

36. Parallel Data Transfer
Flip flops store outputs from combinational logic
Multiple flops can store a collection of data 36

37. Notes Flip flops are powerful storage elements
They can be constructed from gates and latches!
D flip flop is simplest and most widely used
Asynchronous inputs allow for clearing and presetting the flip flop output
Multiple flops allow for data storage
The basis of computer memory!
Combine storage and logic to make a computation circuit
Next time: Analyzing sequential circuits.
credential:
bring a computer
die photo
wafer :
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

38. Must know items Understanding flip flop state:
Stored values inside flip flops
Clocked sequential circuits:
Contain flip flops
Representations of state:
State equations
State table
State diagram
Finite state machines
Mealy machine
Moore machine

39. Flip Flop State y(t) = x(t)Q1(t)Q0(t) Q0(t+1) = D0(t) = x(t)Q1(t)
Behavior of clocked sequential circuit can be determined from inputs, outputs and FF state
y(t) = x(t)Q1(t)Q0(t)
Q0(t+1) = D0(t) = x(t)Q1(t)
Q1(t+1) = D1(t) = x(t) + Q0(t) x Q1 Q0 D Q Q’ y D0 D1
Clk

40. Output and State Equations
Next state dependent on previous state.
y(t) = x(t)Q1(t)Q0(t)
Q0(t+1) = D0(t) = x(t)Q1(t)
Q1(t+1) = D1(t) = x(t) + Q0(t) x Q1 Q0 D Q Q’ y D0 D1
Clk
Output equation
State equations

41. State Table
Sequence of outputs, inputs, and flip flop states enumerated in state table
Present state indicates current value of flip flops
Next state indicates state after next rising clock edge
Output is output value on current clock edge
0 0
0 1
1 0
1 1
Present
State
Next State
x=0 x=1
Q1(t) Q0(t) Q1(t+1) Q0(t+1)
Output
State Table

42. State Table All possible input combinations enumerated
All possible state combinations enumerated
Separate columns for each output value.
Sometimes easier to designate a symbol for each state.
Present
State
Next State
x=0 x=1
s s
s s
s s
s s
Output s0 s1 s2 s3
Let:
s0 = 00
s1 = 01
s2 = 10
s3 = 11

43. State Diagram Circles indicate current state
Arrows point to next state
For x/y, x is input and y is output
0 0
0 1
1 0
1 1
Present
State
Next State
x=0 x=1
Output 11
1/1
0/0
0/0 00 01
0/0 10
1/0
1/0
0/0
1/0

44. State Diagram s1 s2 s0 s3 Each state has two arrows leaving
One for x = 0 and one for x = 1
Unlimited arrows can enter a state
Note use of state names in this example
Easier to identify s1 s2 s0
0/0
1/0 s3
1/1
1/0

45. Flip Flop Input Equations
Boolean expressions which indicate the input to the flip flops. x D0 Q0 Q1 Q D Q’ y Q Q1 D Q0 Q’ D1
Clk
DQ0 = xQ1
DQ1 = x + Q0
Format implies type of flop used

46. Analysis with D Flip-Flops
Identify flip flop input equations
Identify output equation
Note: this example
has no output

47. Mealy Machine present state Output based on state and present input
Comb.
Logic
Comb.
Logic
Q(t+1)
Flip
Flops
next
state
Q(t)
Y(t)
present
state
X(t)
present
input
clk 47

48. Moore Machine Output based on state only Comb. Logic Y(t) Comb. Q(t+1)
Flip
Flops
next
state
Q(t)
present
state
X(t)
present
input
clk 48

49. Mealy versus Moore 49

50. State Diagram with One Input & One Mealy Output
Mano text focuses on Mealy machines
State transitions are shown as a function of inputs and current outputs.
e.g. 1
0/0
Input(s)/Output(s) shown in transition
1/1 S1
1/0 S4 S2
0/0
0/0
0/0
1/0 S3
1/0 50

51. State Diagram with One Input & a Moore Output
Moore machine: outputs only depend on the current state
Outputs cannot change during a clock pulse if the input variables change
Moore Machines usually have more states.
No direct path from inputs to outputs
Can be more reliable 51

52. Designing Finite State Machines
Specify the problem with words
(e.g. Design a circuit that detects three consecutive 1 inputs)
Assign binary values to states
Develop a state table
Use K-maps to simplify expressions
Flip flop input equations and output equations
Create appropriate logic diagram
Should include combinational logic and flip flops

53. Example: Detect 3 Consecutive 1 inputs
State S0 : zero 1s detected
State S1 : one 1 detected
State S2 : two 1s detected
State S3 : three 1s detected
Note that each state has 2 output arrows
Two bits needed to encode state

54. State Table for Sequence Detector
Present
State
Sequence of outputs, inputs, and flip flop states enumerated in state table
Present state indicates current value of flip flops
Next state indicates state after next rising clock edge
Output is output value on current clock edge
Next
State
Input
Output
A B x A B y
S0 = 00
S1 = 01
S2 = 10
S3 = 11

55. Finding Expressions for Next State and Output Value
Create K-map directly from state table (3 columns = 3 K-maps)
Minimize K-maps to find SOP representations
Separate circuit for each next state and output value

56. Circuit for Consecutive 1s Detector
Note location of state flip flops
Output value (y) is function of state
This is a Moore machine.

57. Concept of the State Machine
Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's
Symbolic State Transition Table
State
Diagram
Encoded State Transition Table
Note: Present state and output are the same value
Moore machine

58. Concept of the State Machine
Example: Odd Parity Checker
Next State/Output Functions
NS = PS xor PI; OUT = PS
D FF Implementation
Timing Behavior: Input

59. Mealy Machine: Output is associated with the state transition
Mealy and Moore Machines
Solution 1: (Mealy)
0/0
Even
Odd
1/1
1/0
0/1 1
Reset
[0]
[1]
Output
Input
Transition
Arc
Output is
dependent only
on current state
O/P is dependent
on current state and
input in Mealy
Solution 2: (Moore)
Mealy Machine: Output is associated with the state transition
- Appears before the state transition is completed (by the next clock pulse).
Moore Machine: Output is associated
with the state
Appears after the state transition
takes place.

60. Vending Machine FSM Step 1. Specify the problem
Deliver package of gum after 15 cents deposited
Single coin slot for dimes, nickels
No change
Design the FSM using combinational logic and flip flops

61. Vending Machine FSM State Diagram Reuse states whenever possible
Symbolic State Table

62. How many flip-flops are needed?
Vending Machine FSM
State Encoding
How many flip-flops are needed?

63. Vending Machine FSM Determine F/F implementation K-map for Open
K-map for D0
K-map for D1
Q1 Q0
D N Q1 Q0 D N

64. Minimized ImplementationQ1 D1 Q1 D
D Q Q0
CLK R Q N
OPEN
Reset N Q0 D0 Q0
D Q
CLK Q1 R Q N
Reset Q1 D
Vending machine FSM implementation based on D flip-flops(Moore).

65. YASE FSM Example: Edge Detector
Bit are received one at a time (one per cycle),
such as: time
Design a circuit that asserts
its output for one cycle when
the input bit stream changes
from 0 to 1.
Try two different solutions.
FSM
CLK IN
OUT

66. State Transition Diagram Solution A
IN PS NS OUT
ZERO
CHANGE
ONE 66

67. Solution A, circuit derivation
IN PS NS OUT
ZERO
CHANGE
ONE

68. Solution B
Output depends non only on PS but also on input, IN
IN PS NS OUT
Let ZERO=0,
ONE=1
NS = IN, OUT = IN PS’
What’s the intuition about this solution?

69. Edge detector timing diagrams
Solution A: output follows the clock
Solution B: output changes with input rising edge and is asynchronous wrt the clock.

70. FSM Comparison Solution B Mealy Machine Solution A
output function of both PS & input
maybe fewer states
asynchronous outputs
if input glitches, so does output
output immediately available
output may not be stable long enough to be useful:
Solution A
Moore Machine
output function only of PS
maybe more state
synchronous outputs
no glitching
one cycle “delay”
full cycle of stable output

71. FSM Recap Both machine types allow one-hot implementations.
Moore Machine
Mealy Machine
Both machine types allow one-hot implementations.

72. FSM Optimization State Reduction: Example: Odd parity checker
Motivation:
lower cost
fewer flip-flops in one-hot implementations
possibly fewer flip-flops in encoded implementations
more don’t cares in next state logic
fewer gates in next state logic
Simpler to design with extra states then reduce later.
Example: Odd parity checker
Moore machine

73. State Reduction State Transition Table NS output PS x=0 x=1 S0 S0 S1 0
“Row Matching” is based on the state-transition table:
If two states
have the same output and both transition to the same next state
or both transition to each other
or both self-loop
then they are equivalent.
Combine the equivalent states into a new renamed state.
Repeat until no more states are combined
NS output
PS x=0 x=1
S0 S0 S
S1 S1 S
S2 S2 S
State Transition Table

74. FSM Optimization Merge state S2 into S0 Eliminate S2
New state machine shows same I/O behavior
Example: Odd parity checker.
NS output
PS x=0 x=1
S0 S0 S
S1 S1 S
State Transition Table

75. Row Matching Example State Transition Table NS output
PS x=0 x=1 x=0 x=1
a a b
b c d
c a d
d e f
e a f
f g f
g a f
State Transition Table

76. Row Matching Example NS output PS x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0
c a d
d e f
e a f
f e f
Reduced State Transition Diagram
NS output
PS x=0 x=1 x=0 x=1
a a b
b c d
c a d
d e d
e a d

77. State Reduction
The “row matching” method is not guaranteed to result in the optimal solution in all cases, because it only looks at pairs of states.
For example:
Another (more complicated) method guarantees the optimal solution:
“Implication table” method:
See Mano, chapter 9.

78. Encoding State Variables
Option 1: Binary values
000, 001, 010, 011, 100 …
Option 2: Gray code
000, 001, 011, 010, 110 …
Option 3: One hot encoding
One bit for every state
Only one bit is a one at a given time
For a 5-state machine
00001, 00010, 00100, 01000, 10000

79. State Transition Diagram Solution B
IN PS NS OUT
ZERO
CHANGE
ONE
How does this change the combinational logic?