1. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst Constructing a Computer Creating a general purpose computing device involves a lot of logic Putting together an entire processor at the gate-level isn’t very feasible For the next set of classes, we’ll put together a toolbox of useful logic circuits that we can use in our processor: –Multiplexors –Arithmetic-Logic Unit ( ALU ) –Registers –Memories

2. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst State Logic – D Flip-Flop A state element that is edge-sensitive –Want changes in output ONLY on the transition of the Clk signal from 0  1 (or from 1  0) D Q Q positive edge-triggered flip-flop

3. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst Timing of Master-Slave D Flip-Flop Changes to Q occur only on the positive edge of the Clock D Clock Q D Q Q positive edge-triggered flip-flop time 

4. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst Changes in input values are reflected immediately (subject to the speed of light and electrical delays) on the outputs Each gate has an associated “electrical delay” Delays are often ignored for the purpose of the logic design (but not for the real implementation!) As soon as inputs change, the outputs change – no memory of what happened before –(at least conceptually) Combinational Logic

5. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst Converting Boolean Algebra into Gates C = SA + SB What does this device do? A steering device: S steers/switches A or B onto the output C

6. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst C = SA + SB This is a 2x1 MUX “Block box” version is 2 input by 1 bit of data multiplexor (steering device) –2 inputs requires a 1 bit selector S 2x1 MUX (Multiplexor) S B A C 0 1 S B A C 0 1 S B A C 0 1

7. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst ALU = Arithmetic Logic Unit –A combinational logic device that performs arithmetic and logic operations on a set of inputs (in most cases, 2) –Not clocked – slowed only by electrical delays (combinational logic) For example, if we require 4 operations: –ADD –SUB –AND –OR 1-Bit ALU

8. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst 1-Bit ALU (AND and OR) AND an OR are simple to implement! Need 1 bit of control to select between the two operations

9. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst The addition of two 1 bit inputs: What is the logic circuit for this? ABSumCarry out 0000 0110 1010 1101 1 Bit Binary Addition

10. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst –The combinational logic for Sum (S) is or –The combinational logic for Carry out (C) is –These two portions together is called a “half-adder”: 1 Bit Binary Addition

11. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst Hypothetical How would I add together two 4-bit numbers? String them together –Need some mechanism for carries

12. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst The addition of another 1 bit input: Carry-in Carry inABSumCarry out 00000 00110 01010 01101 10010 10101 11001 11111 1 Bit Binary Addition

13. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst S = Cin A B + Cin A B + Cin A B + Cin A B = Cin(A B + A B) + Cin (A B + A B) = Cin (A  B) + Cin (A  B) = Cin  (A  B) = Cin  A  B Cout = Cin A B + Cin A B + Cin A B + Cin A B = A B + B Cin + A Cin(the “majority” function) 1 Bit Binary Addition

14. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst The combinational logic for Sum (S) is The combinational logic for Carry Out (C) is The result is called a “full-adder”: 1 Bit Binary Addition

15. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst You can design a full-adder using only 2 half-adders and a minimum of additional gates 1 Bit Binary Addition using HAs Only

16. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst Computing S = A + B where A, B, and S are all 4-bit values Use a “cascade” of full-adders [A3:A0] and [B3:B0] are the 4 bit inputs (A3 is the MSB of A, and A0 is the LSB of A) LSB Cin  0 4-Bit Addition Detecting Overflow?

17. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst Overflow = Cin  Cout of the full adder corresponding to the MSB Detecting Overflow

18. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst Computing C = A - B where A, B, and C are all 4-bit values Note: C = A + (B + 1) Inputs need to be A and B LSB Cin  1 4-Bit Subtraction

19. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst 4 operations we wanted to implement: –ADD –SUB –AND –OR 4 operations require a 2 bit selector 1-Bit ALU Revisted

20. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst A 4x1 MUX provides for 4 1-bit inputs (A,B,C,D) and a single 1-bit output 4 inputs requires 2 select bits (S1 and S0) S1:S0 steer one of four inputs onto a single 1-bit output line Function table: S1S0Output 00A 01B 10C 11D 4x1 MUX

21. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst Requires: –4x1 MUX –2x1 MUX –1 FA –1 AND –1 OR –1 NOT Design of a 1-Bit ALU 00 01 10 11 FA A B Cin C1C0 Cout 0 1 C2 4x1MUX

22. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst C2:C1:C0 are the 3 control bits used to select the desired operation All other “control” combinations are unspecified C2C1C0ALU op 000A and B 001A or B 010A + B 110A – B Function Table for 1-Bit ALU

23. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst 1-Bit ALU – Black Box 1-BitALU A B Cin C2C1C0 Result Cout

24. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst Points to ponder: –When C2:C1:C0 = 000, what is happening on “ports” 1, 2, and 3 of the 4x1 MUX? –Recall that an ALU is a combinational circuit – what does this really mean? –When C2 = 1 (and the LSB Cin = 1), the FA is subtracting –C2 = 1 for sub only ALU Design Issues

25. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst How to connect the 4 1-bit ALUs? Cout of previous connects to Cin of next Cin of LSB connected to C2 for for proper add/sub selection Designing a 4-Bit ALU

26. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst “zero-detect” implemented as “nor” of all result bits: ZD = 1 if result = 0000 ZD is useful for implementing conditional branches (BNE and BEQ) Completed 4-Bit ALU

27. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst Suppose the ALU function table had been defined initially as follows. Try to “fix” the 1- bit ALU using a minimum amount of new hardware. C2C1C0ALU op 110A and B 011A or B 101A – B 111A + B Test Yourself

28. CS 352 : Computer Organization and Design University of Wisconsin-Eau Claire Dan Ernst Requires: –4x1 MUX –2x1 MUX –1 FA –1 AND –1 OR –1 NOT Design of a 1-Bit ALU 00 01 10 11 FA A B Cin C1C0 Cout 0 1 C2 4x1MUX