1. IKI10201 06c-Synthesis of Sequential Logic Bobby Nazief Semester-I 2005 - 2006 The materials on these slides are adopted from: Prof. Daniel Gajski’s transparency for Principles of Digital Design.

2. 2 Analyze this!

3. 3 Remember: sequential circuit analysis To analyze sequential circuits, you have to: – Find Boolean expressions for the outputs of the circuit and the flip- flop inputs. – Use these expressions to fill in the output and flip-flop input columns in the state table. – Finally, use the characteristic equation or characteristic table of the flip-flop to fill in the next state columns. The result of sequential circuit analysis is a state table or a state diagram describing the circuit.

4. 4 The Analysis

5. 5 Finite State Machine (FSM) Model Quintuple – S: set of states – I: set of inputs – O: set of outputs – f: next-state function (S x I  S) – h: output funtion state-based (Moore Machine): S  O input-based (Mealy Machine): S x I  O

6. 6 Moore Machine

7. 7 Mealy Machine

8. 8 FSM Implementations

9. 9 Synthesis of sequential logic

10. 10 The Case: Modulo-3 Up-Down Counter

11. 11 FSM Model Capture

12. 12 FSM Model Capture (cont.)

13. 13 FSM Model Capture (cont.)

14. 14 State Minimization Reduce the number of states – reduce the number of flip-flops Based on behavioral equivalence concept – 2 FSMs are equivalent if they produce the same sequence of output symbols for every sequence of input symbols s 1 & s 2 states in an FSM are equivalent, iff: – for every input symbol i, h(s 1, i) = h(s 2, i) – for every input symbol i, f(s 1, i) = f(s 2, i) Minimization procedure: 1. partition states into equivalence classes 2. construct new FSM with one state for each equivalence class

15. 15 State Minimization (cont.) output values next states

16. 16 State Minimization (cont.) State minimization can also be done using Implication Table (see text!)

17. 17 State Encoding The cost & delay of FSM implementation depends on encoding of symbolic states. – e.g., 4 states can be encoded in 4! = 24 different ways There are more than n! different encodings for n states. – exploration of all encodings is impossible, therefore heuristics are used 3 different heuristics: 1. minimum-bit change 2. prioritized adjacency 3. hot-one encoding

18. 18 State Encoding (cont.) Minimum-bit change: assigns codes to states so that the total number of bit changes for all state transitions is minimized.

19. 19 State Encoding (cont.) Prioritized adjacency: assigns adjacent encodings to all states with common source, common destination, or common output – Highest: states with the same next-state since the same next- state code will appear in adjacent entries in the K-map – Second: the next-states of the same state since they also may appear adjacent in the K-map – Third: states that have the same output value for the same input value since they may be adjacent in the output K-map

20. 20 State Encoding (cont.) Possible state encoding for module-3 counter: – A: minimum-bit change/prioritized adjacency – B: simplified output logic – C: Hot-one encoding

21. 21 State Encoding (based on Encoding A)

22. 22 Choice of memory elements Select the type of flip-flops from: D, SR, JK, T Derive the required flip-flop’s input value for every present-next state pair; then derive the excitation equations: J 1 K 1 J 0 K 0 J 1 = Q 0 ’CD + Q 0 CD’ = (C’ + Q 0 D + Q 0 ’D’) K 1 = C J 0 = Q 1 CD + Q 1 ’CD’ = (C’ + Q 1 ’D + Q 1 D’) K 0 = C

23. 23 The Circuit: Modulo-3 Up-Down Counter