1. Lecture 5. AT91 - Memory Map, Timers, and AIC -
ECM586 Special Topics in Embedded Systems
Lecture 5. AT91
- Memory Map, Timers, and AIC -
Prof. Taeweon Suh
Computer Science Education
Korea University

2. Program Execution in CPU
ARM (CPU)
PC (R15) R0 R1 R2 R3
R14
R15 …
32 bits
Registers
0x0000
0x0000
0x0004
0x0004
0x0008
0x0008
Memory
Address Bus 0x 0x 0x 0x
0x0018
0x0014
0x0008
0x0004
0x0000 +
0x0018
0x0014 0x 0x 0x
Data Bus
add r2, r2, r3
ldr r3, [r5]
ldr r2, [r4]
add r2 ,r2, r3
ldr r3, [r5]
ldr r2, [r4]

3. Memory in Graphics card
Memory Map
Memory map indicates how memory space is laid out
Examples:
Where the main memory is located in the memory space
Where I/O devices are located in the memory space
Memory-mapped I/Os: To access registers in I/O devices, CPU should access a memory space allocated for the I/O devices
Memory map depends on the size of the address bus
If address bus is 32-bit wide, memory space is 4GB
If address bus is 48-bit wide, memory space is 256TB
Suppose that the address bus is 32-bit wide
0xFFFF_FFFF
Memory Space
BIOS ROM
CPU
North Bridge
South Bridge
Main Memory
(DDR)
FSB
(Front-Side Bus)
DMI
(Direct Media I/F)
0xE000_0000
0x7FFF_FFFF
Memory in Graphics card
0x7000_0000
Main memory
(1GB)
0x3FFF_FFFF
Byte address 0x

4. Memory Map in AT91 Memory Map is mostly defined by hardware provider
Like you need a map to find places, CPU needs “map” to access memory or hardware devices
Depending on CPU, the size of the memory map is determined
For example:
if your CPU is 32-bit CPU, it would have 4GB (232) memory space (memory map)
If your CPU is 64-bit CPU, it would have 16EB (264)?
Yeah, but it depends on how many physical address lines come out of CPU..

5. On-chip Peripheral Map in AT91

6. AT91 Block Diagram CPU provide ISA (Instruction Set Architecture)
ISA means instructions CPU provides
If you are programming directly with instructions, you are doing assembly programming
After compiling your assembly program, the linker combines objects and library files, relocates their code and data and tie up symbol references

7. Linker Script Example Open “Makefile” in lab 2
“make” utility makes your life easier
Default input file for “make “is “Makefile”
Type “man make” to see the detailed info in Linux or Google-search it with, for example, “make linux”
“ld” is the GNU linker and “arm-linux-ld” is the GNU linker for ARM cross-compilation
The final binary (=executable) “timerirq” in the following case contains information about where (which address) your code and data are located

8. Example Linker Script Check out the Lab source code Hello.lds
This script locates your program (text) from address 0x0000_0000, where ROM is located
Data section in your program is located, aligned at 8KB (8192) boundary

9. Program Execution Path in H/W
ARM
CPU core
Address Bus
EAX
R15 ….
ALU R1 R0
32-bit
0x003F_FFFC
0x003F_FFF8
0x0000_0020
…..
0x0000_0004
0x0000_0000
ROM
32-bit
ldr sp, irq_stack (=E59F_D08C)
msr CPSR, … (=E321_F0D2)
Data Bus
B (=EAFF_FFFE)
B reset (=EA00_0006)

10. Interrupt Enable Register (0x24)
Timers in AT91
There are 3 counter channels in AT91
2 modes of operation: Capture mode and Waveform mode
clock
16-bit counter
(incrementing) ?
Register A (RA) (0x14) ?
Register B (RB)
(0x18)
Reset
1. SWTRG: TC_CCR (0x00)
2. SYNC: external signal
3. RC: if RC == counter value ?
Register C (RC)
(0x1C)
Counter Value (0x10)
Status Register (0x20)
Interrupt Enable Register (0x24)
Base Address: 0xFFFE_0000
Status Register: RA, RB, RC compare status etc

11. Capture Mode in Timers (AT91)
TIOA
Capture the counter value
at which edge of TIOA (LDRA in TC_CMR)
clock
16-bit counter
(incrementing) ?
Register A (RA) (0x14)
Capture the counter value at which edge of TIO (LDRB in TC_CMR)
Register B (RB)
(0x18)
reset ?
Register C (RC)
(0x1C)
WAVE = 0 in TC_CMR (0x04)
Counter Value (0x10)
Status Register (0x20)
Interrupt Enable Register (0x24)
RC Compare Interrupt

12. Waveform Mode in Timers (AT91)
TIOA
clock
16-bit counter
(incrementing) ?
Register A (RA) (0x14)
TIOB
Register B (RB)
(0x18)
Waveform
(PWM: Pulse
Width
Modulation)
reset ?
Register C (RC)
(0x1C)
WAVE = 1 in TC_CMR (0x04)
Counter Value (0x10)
Status Register (0x20)
Interrupt Enable Register (0x24)
RA, RB, RC Compare Interrupts

13. Interrupt Controller (INTC)
Typically, a computer system (including embedded systems) has an interrupt controller
x86-based computer system (general-purpose computer system) has 3 interrupt controllers!
Local APIC (Advanced Programmable Interrupt Controller)
I/O APIC
8259
Interrupt controller receives interrupt requests from I/O devices and sends a interrupt signal to CPU
x86 allocates 2 input pins for interrupt: INTR, NMI
ARM provides 2 input pins as well: nIRQ, nFIQ
Interrupt controller provides registers with which programmers can
Assign priority to each interrupt source
Mask specific interrupt inputs

14. INTC in a System … … … nIRQ Priority Control ARM Interrupt Masking
SoC (System-on-a-Chip)
External Inputs (Keyboard)
Serial Port (UART)
Interrupt Controller
nIRQ
nFIQ
Timers
ARM
Priority Control
Interrupt Masking …
Watchdog Timer … …
Wireless NIC (Network I/F Card)

15. AIC (Advanced Interrupt Controller) in AT91
Base Address: 0xFFFF_F000
Set Priority
US0_IRQ
nIRQ
SMR 0 (0x000)
Source Vector Register 0 (0x080)
US1_IRQ
nFIQ
SMR 1 (0x004)
Source Vector Register 1 (0x084)
TC0_IRQ
SMR 2 (0x008)
Source Vector Register 2 (0x088)
TC1_IRQ
IRQ Vector Reg (0x100)
…..
…..
TC2_IRQ
FIQ Vector Reg (0x104)
SMR 29 (0x074)
Source Vector Register 29 (0x0F0)
IRQ0_IRQ
SMR 30 (0x078)
Source Vector Register 30 (0x0F8)
IRQ1_IRQ
SMR 31 (0x07C)
Source Vector Register 31 (0x0FC)
IRQ2_IRQ
Interrupt Enable Reg (0x120)
End of Interrupt Reg (0x130)