1. C.S. Choy95 COMPUTER ORGANIZATION Logic Design Skill to design digital components JAVA Language Skill to program a computer Computer Organization Skill to build a computer

2. C.S. Choy96 PROGRAMMING The interface to make a computer to perform a task. The part of the computer that actually executes the “program” is the microprocessor or central processing unit, CPU. CPU is a digital component that execute instructions.

3. C.S. Choy97 TYPES OF INSTRUCTIONS Data Transfer Instructions Move data from one place to another including REGISTERS MEMORIES I/O DEVICES Data Operation Instructions Perform operations using one or two data and store the result. Operations include ARITHMETIC LOGIC SHIFT (one data) Program Control Instructions Change the sequence of operations (consecutive instruction flow) conditionally or non-conditionally Others INTERRUPT HALT

4. C.S. Choy98 INSTRUCTION CODES A binary pattern in a specific format. Example of a microprocessor which has a simple instruction set.

5. C.S. Choy99 LEVELS OF PROGRAMMING LANGUAGES High-level – platform independent C++ JAVA FORTRAN Assembly Language – microprocessor dependent Instruction mnemonics representing individual instruction codes Machine Language – microprocessor dependent Actual instruction codes

6. C.S. Choy100 COMPILING AND ASSEMBLING

7. C.S. Choy101 JAVA COMPILATION PROCESS

8. C.S. Choy102 HISTORY OF COMPUTER DEVELOPMENT ABACUS, Difference Machine (mechanical) UNIVAC ENIAC (electronic numerical integrator and computer) 1946 MICROPROCESSOR 1971 MAINFRAME WORKSTATION DESKTOP 1980s (IBM PC) INTEL and MICROSOFT SUPER-COMPUTER (multi-processors)

9. source: Modern MediaC.S. Choy103 A PC

10. C.S. Choy104 GENERIC COMPUTER ORGANIZATION

11. C.S. Choy105 Address Bus Specify a memory location for access by CPU Data Bus Data channel between CPU and other components Control Bus A collection of individual control signals e.g. a signal to indicate whether a data is to be read into or written out of CPU A system may have a hierarchy of buses. For example, it may use its address, data, and control buses to access memory, and an I/O controller. The I/O controller, in turn, may access all I/O devices using a second bus, often called an I/O bus or a local bus. e.g. PCI bus SYSTEM BUSES

12. C.S. Choy106 The procedure a microprocessor goes through to process an instruction. FETCH DECODE EXECUTE e.g. Fetch / Memory Read Operation Memory Mapped I/O – CPU accesses an I/O device as a memory Isolated I/O – CPU has a separate control signal to indicate an I/O read/write INSTRUCTION CYCLE

13. C.S. Choy107 Register Section Register directly accessible by programs – registers to store operands Register not directly accessible by programs – program counter instruction register Control Unit The digital circuit that dictates the action sequence of CPU Sequential circuit – finite state machine Combinational circuit – instruction decoder Arithmetic/Logic Unit Perform the arithmetic and logic operations CPU INTERNAL ORGANIZATION

14. C.S. Choy108 TYPES OF MEMORY Read Only Memory, ROM Data can only be read and will not be changed even power is off Masked ROM Programmable ROM, PROM Erasable PROM, EPROM Electrically Erasable PROM, E 2 PROM Flash E 2 PROM – electrically erasable in blocks of data Random Access Memory, RAM Used to store data that changes. As long as power is on, data is kept Dynamic RAM, DRAM – require refresh, slower Static RAM, SRAM – no refresh, faster

15. C.S. Choy109 Linear e.g. 8x2 Two-Dimensional e.g. 8x2 MEMORY ORGANIATION Simpler decoders are used instead. For a symmetrical two-dimensional array, Two n/2 to 2 n/2 decoders O(2 1+n/2 ) e.g. 4K x 1 ROM 2D requires 3% of Linear N to 2 n decoder O(2 n )

16. C.S. Choy110 Wider Word Length Larger Memory Size high-order interleavinglow-order interleaving MEMORY SUBSYSTEM CONFIGURATION

17. C.S. Choy111 CONTROL LOGIC FOR MEMORY CHIP e.g. 8x4 memory subsystem constructed from two 8x2 memory chips in a 6-bit address bus

18. C.S. Choy112 MULTIBYTE DATA ORGANIZATION Many data formats are longer than one data word/byte (bit- length of the data bus) so require more than one memory location for storage. It is necessary to define the order of the data in these locations Big EndianLittle Endian

19. C.S. Choy113 OTHER MEMORY SUBSYSTEMS Cache Memory Cache memory can be accessed much faster than normal memory chip, and is usually integrated inside a processor chip Virtual Memory A permanent storage device (harddisk) is used as a part of the computer’s memory, expanding the memory space of the computer while minimizing cost

20. C.S. Choy114 CPU accesses I/O devices as memories. However, I/O devices can be vastly different in speed and behavior, so an interface circuit is required Generic Interface for an Input Device Enable Logic I/O SUBSYSTEM ORGANIZATION

21. C.S. Choy115 I/O SUBSYSTEM ORGANIZATION Generic Interface for an Output Device Enable Logic I/O Device

22. C.S. Choy116 I/O devices are usually much slower than CPU. For this reason, they can have timing problem when interfacing with CPU. To solve this problem, most CPUs have a control input signal called READY. The CPU goes into WAIT state when READY is asserted. An alternative is to use INTERRUPT. An interrupt will direct the attention of the CPU to a self-contained program (interrupt service routine) and return the CPU to its main program after completion. There are situations where a large amount of data are to be channeled between I/O devices and memory. It will tie up CPU too much if the transfer has to go through CPU. Direct Memory Access, DMA, is a method used to by-pass CPU in these transfers. I/O SUBSYSTEM ORGANIZATION

23. C.S. Choy117