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2. hardware and operating systems basics

3. BY SA

7. client/workstation (PC) server (responds to requests from network) hand-held (phone, audio player) embedded system (toaster, car) mainframe (a big server) supercomputer (a many-processor system)

8. RAM (Random Access Memory) addressable by the CPU volatile faster than storage code and data of running programs

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10. programming model (simplified conception of a processor for sake of programmers)

11. instruction (a sequence of bits understood by the processor to signal a certain action) copy bytes arithmetic bit logic jumps

12. register (a small memory area in a processor) status general purpose

13. ISA (Instruction Set Architecture) x86 (IA-32, x86-64) ARM MIPS Motorola 68k

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15. call stack (local variables) call stack (local variables) program memory heap (everything else) heap (everything else) code

16. frame of main frame of cat frame of dog frame of fish frame of bird frame of lama stack space local variables argument values  top of stack

17. frame of moose stack space frame of main frame of cat frame of dog frame of fish frame of bird local variables argument values return address  top of stack

18. big-endian vs. little-endian (the order in which the bytes of a register are copied from registers to memory and vice versa)

19. big-endian vs. little-endian (the order in which the bytes of a register are copied from registers to memory and vice versa)

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21. processor registers processor cache random access memory hard drives speed, cost capacity

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23. CPU registers device read/write 

24. port-mapped I/O vs. memory-mapped I/O output register 2 to port 0x44 98 copy register 5 to address 0x66 2C 1A 32

25. ports memory addresses RAM 0x00 00 00 00 0xFF FF FF FF byte 0 byte n port 0 port n devices

26. memory addresses RAM 0x00 00 00 00 0x00 01 00 00 0xFF FF FF FF 0x00 00 FF FF byte 0 byte n devices

27. (code periodically checks device registers to see if the device needs the CPU to do something) polling

28. CPU registers device interrupt line

29. (code periodically checks device registers to see if they need the CPU to do something) polling 1.device sends interrupt signal to CPU 2.CPU saves state of whatever it was currently doing 3.CPU jumps to address corresponding to interrupt number in the interrupt table interrupt

30. 0x76 00 00 00interrupt 0 0x20 15 10 00interrupt 1 0x82 87 95 94interrupt 2 0xA2 22 00 10interrupt 3 0xFF 31 21 14interrupt 4 0xFF 31 01 11interrupt 5 0xFF 90 44 44interrupt 6 0xFF 31 01 11interrupt 7 ……

31. (code periodically checks device registers to see if they need the CPU to do something) polling 1.device sends interrupt signal to CPU 2.CPU saves state of whatever it was currently doing 3.CPU jumps to address corresponding to interrupt number in the interrupt table 4.CPU returns to whatever it was doing before the interrupt interrupt

32. hardware exception (a condition which causes the CPU to jump to a pre-determined address) 0x76 00 00 00exception 0 0x20 15 10 00exception 1 0x82 87 95 94exception 2 0xA2 22 00 10exception 3 0xFF 31 21 14exception 4 ……

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34. Instruction Set Architecture byte size word size address size cache speeds and sizes big-endian vs. little-endian ports vs. memory-mapped i/o number of processors/cores

35. boot firmware CPU registers BIOS

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37. boot firmware CPU registers BIOS

38. operating system (manages the hardware and running programs) load and manage processes provide “interfaces” to hardware via system calls provide a filesystem provide a basic user interface

39. Windows (series of OS’s from Microsoft) Windows 7 Windows Server 2008 Windows CE

40. Unix (a family of OS’s) Linux BSD OS X

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42. OS device driver (plug-in to the OS to control a particular device) device driver software hardware

43. B B A A B B C C C C B B A A B B A A time A A B B C C B B C C A A C C C C CPU CPU 2 process OS

44. 1.CPU receives interrupt 2.interrupt stores state of currently running code 3.interrupt invokes handler 4.interrupt handler invokes the scheduler 5.scheduler selects a process 6.scheduler “configures” CPU for that process 7.scheduler jumps execution to that process pre-emptive multitasking

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46. Process C Process B OS Process A 0x00 00 00 00 0xFF FF FF FF

47. stack heap code 0x 00 00 00 00 0x FF FF FF FF heap RAM byte 0 byte n

48. stack heap code 0x 00 00 00 00 0x FF FF FF FF heap RAM byte 0 byte n HD

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50. Process C Process B OS Process A jump to system call code via special instruction RAM

51. 0x76 00 00 00system call 0 0x20 15 10 00system call 1 0x82 87 95 94system call 2 0xA2 22 00 10system call 3 0xFF 31 21 14system call 4 0xFF 31 01 11system call 5 0xFF 90 44 44system call 6 0xFF 31 01 11system call 7 ……

52. stack code 0x 00 00 00 00 0x FF FF FF FF heap allocated with system call  heap allocated with system call 

53. stack code 0x 00 00 00 00 0x FF FF FF FF heap  deallocated with system call

54. stack code 0x 00 00 00 00 0x FF FF FF FF  top of stack stack boundary  heap

55. stack code 0x 00 00 00 00 0x FF FF FF FF  top of stack stack boundary  heap

56. created waitingrunning blocked terminated

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58. HD partition 1 partition 2 partition 3 HD partition 4 flash drive partition 5 CD-ROM partition 6 partition 7

59. file 35 file 7 file 61 file 3 directory 21 directory 86 root directory

60. partition 1 C:H:H:D:D: C:/ H:/ D:/ partition 2 partition 3

61. partition 1 C:H:H:D:D: C:/adams/nixon H:/taylor/polk/hayes D:/garfield partition 2 partition 3

62. partition 1 /banana//lemon/apple partition 2 partition 3

63. partition 1 /banana//lemon/apple /banana/adams/nixon /taylor/polk/hayes /lemon/apple/garfield partition 2 partition 3

64. IPC (Interprocess Communication) files pipes sockets signals shared memory

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