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CoolRunner™-II Advanced Features - II. Quick Start Training Advanced CoolRunner-II Techniques-II On the Fly Reconfiguration (OTF) – Understanding OTF.

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Presentation on theme: "CoolRunner™-II Advanced Features - II. Quick Start Training Advanced CoolRunner-II Techniques-II On the Fly Reconfiguration (OTF) – Understanding OTF."— Presentation transcript:

1 CoolRunner™-II Advanced Features - II

2 Quick Start Training Advanced CoolRunner-II Techniques-II On the Fly Reconfiguration (OTF) – Understanding OTF – OTF Applications DataGATE – Understanding DataGATE – DataGATE Applications

3 Quick Start Training On the Fly Reconfiguration (OTF) OTF exploits the RealDigital cell architecture Initial pattern is loaded into a configuration shifter The pattern first transfers into nonvolatile memory The pattern is then read from NV to SRAM for actual cell operation Leaves ability to reload the NV memory as we say, “On the Fly”

4 Quick Start Training CoolRunner-II High Level Architecture

5 Quick Start Training Behind the Scenes Configuration Memory

6 Quick Start Training Reconfiguration Process Nonvolatile Cell Volatile Cell

7 Quick Start Training Reconfiguration Process Blank Initial Condition

8 Quick Start Training Reconfiguration Process Pattern 1 Blank Nonvolatile Programmed with Pattern 1

9 Quick Start Training Reconfiguration Process Pattern 1 Both programmed with Pattern 1

10 Quick Start Training Reconfiguration Process Pattern 2Pattern 1 Pattern 1 in Volatile Pattern 2 in Nonvolatile

11 Quick Start Training Reconfiguration Process Pattern 2 Pattern 2 in Both

12 Quick Start Training WebPACK ISE5.2i Supports iMPACT utility that permits OTF updates User loads first pattern, then “inits” the part Second pattern load occurs while first one runs Init can be issued at any time the user wishes After 50-100 microseconds, new pattern is running Its that easy!

13 Quick Start Training iMPACT Menu

14 Quick Start Training Selecting the OTF

15 Quick Start Training OTF Applications Uploading FPGA and changing function Building small tables in Function Blocks Changing PicoBlaze instructions Changing keys on stream ciphers Board level testing

16 Quick Start Training Configure FPGA then Handle Interrupts At power up CPLD configures FPGA (SelectMap JEDEC) FPGA active,CPU configures CPLD w. Interrupt JEDEC CPLD active, CPU configures CPLD w. SelectMap JEDEC System can be power cycled as needed FPGA Bitstream CR-II FPGA CPU Interrupt JEDEC SelectMap JEDEC 3 JTAG Select Map

17 Quick Start Training Small Tables CoolRunner-II CPLD has multiple Function Blocks Each Function Block has Programmable Logic Array (PLA) PLA can also create “miniEPROM” or a table Can reprogram OTF Tables can hold constants, perform arithmetic, etc. FB AIM

18 Quick Start Training Reloading an Instruction Set See PicoBlaze demonstration to see this in action!

19 Quick Start Training Re-Keying a Stream Cipher Encryption can be done with Linear Feedback Shift Registers (LFSR) Seed values and tap points can be changed OTF EX-OR Clear Bits to Encrypt Changing “key” can be done while the part operates Fancy LFSRs exist for better results (see Security presentation for detail) D Q LFSR Clear Bits Encrypted Bits

20 Quick Start Training Board Testing Test patterns from CPLD drive/respond to other chips on board CPLD is updated via JTAG from off/on board CPU CPLD assumes different function when not testing board PCB

21 Quick Start Training DataGATE Initially defined as power saving feature – Block freely switching input signals – Can turn off clocks Other applications arrived – Hot plugging – Debugging – Security

22 Quick Start Training DataGATE Assertion Rail

23 Quick Start Training DataGATE Input Pin Details Data Latch to AIM DataGATE Assertion Rail Input Pin Configuration Bit

24 Quick Start Training DataGATE Timing

25 Quick Start Training Power Saving with External Pin Control AIM Signal drives low to pass data DataGATE Assertion Rail External signal drives high to enable data flow

26 Quick Start Training Using Internal Timer Signal drives low to pass data DataGATE Assertion Rail External clock to internal timer Timer

27 Quick Start Training Using State Machine Controller Signal drives low to pass data DataGATE Assertion Rail External clock Controller Signal A Signal B State Machine Inputs

28 Quick Start Training Hot Plugging with DataGATE PCB with Logic Rack with Card Slots Electronics on card slots use CoolRunner-II with DataGate DataGATE Switch & Light

29 Quick Start Training Debugging with DataGATE Signal drives low to pass data DataGATE Assertion Rail External clock Debug Trigger Signal A Signal B Debug Trigger Inputs

30 Quick Start Training Security with DataGATE Signal drives low to pass data DataGATE Assertion Rail External clock Password Checker Password PW Strobe Security Inputs

31 Quick Start Training Support Standard WebPACK ISE 5.2 CoolRunner-II Design Kit More details for OTF in XAPP 388 More details for DataGate in XAPP 395 Additional advanced feature details in XAPP 378


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