Instructor: Erol Sahin

Instructor: Erol Sahin
The Memory Hierarchy CENG331: Introduction to Computer Systems 10th Lecture Instructor: Erol Sahin Acknowledgement: Most of the slides are adapted from the ones prepared by R.E. Bryant, D.R. O’Hallaron of Carnegie-Mellon Univ.

Overview Topics Storage technologies and trends Locality of reference
Caching in the memory hierarchy

Random-Access Memory (RAM)
Key features RAM is packaged as a chip. Basic storage unit is a cell (one bit per cell). Multiple RAM chips form a memory. Static RAM (SRAM) Each cell stores bit with a six-transistor circuit. Retains value indefinitely, as long as it is kept powered. Relatively insensitive to disturbances such as electrical noise. Faster and more expensive than DRAM. Dynamic RAM (DRAM) Each cell stores bit with a capacitor and transistor. Value must be refreshed every ms. Sensitive to disturbances. Slower and cheaper than SRAM.

SRAM Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. A typical SRAM uses six MOSFETs to store each memory bit. SRAM is more expensive, but faster and significantly less power hungry (especially idle) than DRAM. It is therefore used where either bandwidth or low power, or both, are principal considerations. SRAM is also easier to control (interface to) and generally more truly random access than modern types of DRAM. Due to a more complex internal structure, SRAM is less dense than DRAM and is therefore not used for high-capacity, low-cost applications such as the main memory in personal computers.

DRAM DRAM is usually arranged in a square array of one capacitor and transistor per data bit storage cell. The illustrations to the right show a simple example with only 4 by 4 cells Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. The main memory (the "RAM") in personal computers is Dynamic RAM (DRAM), as is the "RAM" of home game consoles (PlayStation, Xbox 360 and Wii), laptop, notebook and workstation computers. The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. This allows DRAM to reach very high density. Unlike flash memory, it is volatile memory (cf. non-volatile memory), since it loses its data when power is removed. The transistors and capacitors used are extremely small—millions can fit on a single memory chip.

SRAM vs DRAM Summary Tran. Access
per bit time Persist? Sensitive? Cost Applications SRAM 6 1X Yes No 100x cache memories DRAM 1 10X No Yes 1X Main memories, frame buffers

Conventional DRAM Organization
d x w DRAM: dw total bits organized as d supercells of size w bits 16 x 8 DRAM chip cols 1 2 3 memory controller 2 bits / addr 1 rows 2 supercell (2,1) (to CPU) 3 8 bits / data internal row buffer

Reading DRAM Supercell (2,1)
Step 1(a): Row access strobe (RAS) selects row 2. Step 1(b): Row 2 copied from DRAM array to row buffer. 16 x 8 DRAM chip cols memory controller 1 2 3 RAS = 2 2 / addr 1 rows 2 3 8 / data internal row buffer

Reading DRAM Supercell (2,1)
Step 2(a): Column access strobe (CAS) selects column 1. Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU. 16 x 8 DRAM chip cols memory controller 1 2 3 CAS = 1 2 / addr supercell (2,1) To CPU 1 rows 2 3 8 / data supercell (2,1) internal row buffer internal buffer

Memory Modules addr (row = i, col = j) : supercell (i,j) 64 MB
DRAM 0 64 MB memory module consisting of eight 8Mx8 DRAMs 31 7 8 15 16 23 24 32 63 39 40 47 48 55 56 64-bit doubleword at main memory address A bits 0-7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 DRAM 7 64-bit doubleword 31 7 8 15 16 23 24 32 63 39 40 47 48 55 56 64-bit doubleword at main memory address A Memory controller

Enhanced DRAMs All enhanced DRAMs are built around the conventional DRAM core. Fast page mode DRAM (FPM DRAM) Access contents of row with [RAS, CAS, CAS, CAS, CAS] instead of [(RAS,CAS), (RAS,CAS), (RAS,CAS), (RAS,CAS)]. Extended data out DRAM (EDO DRAM) Enhanced FPM DRAM with more closely spaced CAS signals. Synchronous DRAM (SDRAM) Driven with rising clock edge instead of asynchronous control signals. Double data-rate synchronous DRAM (DDR SDRAM) Enhancement of SDRAM that uses both clock edges as control signals. Video RAM (VRAM) Like FPM DRAM, but output is produced by shifting row buffer Dual ported (allows concurrent reads and writes)

Nonvolatile Memories DRAM and SRAM are volatile memories
Lose information if powered off. Nonvolatile memories retain value even if powered off. Generic name is read-only memory (ROM). Misleading because some ROMs can be read and modified. Types of ROMs Programmable ROM (PROM) Erasable programmable ROM (EPROM) Electrically erase PROM (EEPROM) Flash memory Firmware Program stored in a ROM Boot time code, BIOS (basic input/ouput system) graphics cards, disk controllers.

Typical Bus Structure Connecting CPU and Memory
A bus is a collection of parallel wires that carry address, data, and control signals. Buses are typically shared by multiple devices. CPU chip register file ALU system bus memory bus main memory bus interface I/O bridge

Memory Read Transaction (1)
CPU places address A on the memory bus. register file Load operation: movl A, %eax ALU %eax main memory I/O bridge A bus interface A x

Main memory reads A from the memory bus, retrieves word x, and places it on the bus. register file ALU Load operation: movl A, %eax %eax main memory I/O bridge x bus interface A x

CPU read word x from the bus and copies it into register %eax. register file Load operation: movl A, %eax ALU %eax x main memory I/O bridge bus interface A x

Memory Write Transaction (1)
CPU places address A on bus. Main memory reads it and waits for the corresponding data word to arrive. register file Store operation: movl %eax, A ALU %eax y main memory I/O bridge A bus interface A

CPU places data word y on the bus. register file Store operation: movl %eax, A ALU %eax y main memory I/O bridge y bus interface A

Main memory read data word y from the bus and stores it at address A. register file ALU Store operation: movl %eax, A %eax y main memory I/O bridge bus interface A y

Disk Geometry Disks consist of platters, each with two surfaces.
Each surface consists of concentric rings called tracks. Each track consists of sectors separated by gaps. tracks surface track k gaps spindle sectors

Disk Geometry (Muliple-Platter View)
Aligned tracks form a cylinder. surface 0 surface 1 surface 2 surface 3 surface 4 surface 5 cylinder k spindle platter 0 platter 1 platter 2

Disk Capacity Capacity: maximum number of bits that can be stored.
Vendors express capacity in units of gigabytes (GB), where 1 GB = 10^9. Capacity is determined by these technology factors: Recording density (bits/in): number of bits that can be squeezed into a 1 inch segment of a track. Track density (tracks/in): number of tracks that can be squeezed into a 1 inch radial segment. Areal density (bits/in2): product of recording and track density. Modern disks partition tracks into disjoint subsets called recording zones Each track in a zone has the same number of sectors, determined by the circumference of innermost track. Each zone has a different number of sectors/track

Computing Disk Capacity
Capacity = (# bytes/sector) x (avg. # sectors/track) x (# tracks/surface) x (# surfaces/platter) x (# platters/disk) Example: 512 bytes/sector 300 sectors/track (on average) 20,000 tracks/surface 2 surfaces/platter 5 platters/disk Capacity = 512 x 300 x x 2 x 5 = 30,720,000,000 = GB

Disk Operation (Single-Platter View)
The disk surface spins at a fixed rotational rate By moving radially, the arm can position the read/write head over any track. The read/write head is attached to the end of the arm and flies over the disk surface on a thin cushion of air. spindle spindle spindle spindle spindle

Disk Operation (Multi-Platter View)
arm read/write heads move in unison from cylinder to cylinder spindle

Disk Access Time Average time to access some target sector approximated by : Taccess = Tavg seek + Tavg rotation + Tavg transfer Seek time (Tavg seek) Time to position heads over cylinder containing target sector. Typical Tavg seek = 9 ms Rotational latency (Tavg rotation) Time waiting for first bit of target sector to pass under r/w head. Tavg rotation = 1/2 x 1/RPMs x 60 sec/1 min Transfer time (Tavg transfer) Time to read the bits in the target sector. Tavg transfer = 1/RPM x 1/(avg # sectors/track) x 60 secs/1 min.

Disk Access Time Example
Given: Rotational rate = 7,200 RPM Average seek time = 9 ms. Avg # sectors/track = 400. Derived: Tavg rotation = 1/2 x (60 secs/7200 RPM) x 1000 ms/sec = 4 ms. Tavg transfer = 60/7200 RPM x 1/400 secs/track x 1000 ms/sec = 0.02 ms Taccess = 9 ms + 4 ms ms Important points: Access time dominated by seek time and rotational latency. First bit in a sector is the most expensive, the rest are free. SRAM access time is about 4 ns/doubleword, DRAM about 60 ns Disk is about 40,000 times slower than SRAM, 2,500 times slower then DRAM.

Logical Disk Blocks Modern disks present a simpler abstract view of the complex sector geometry: The set of available sectors is modeled as a sequence of b-sized logical blocks (0, 1, 2, ...) Mapping between logical blocks and actual (physical) sectors Maintained by hardware/firmware device called disk controller. Converts requests for logical blocks into (surface,track,sector) triples. Allows controller to set aside spare cylinders for each zone. Accounts for the difference in “formatted capacity” and “maximum capacity”.

I/O Bus CPU chip register file ALU system bus memory bus main memory
bus interface I/O bridge I/O bus Expansion slots for other devices such as network adapters. USB controller graphics adapter disk controller mouse keyboard monitor disk

Reading a Disk Sector (1)
CPU chip CPU initiates a disk read by writing a command, logical block number, and destination memory address to a port (address) associated with disk controller. register file ALU main memory bus interface I/O bus USB controller graphics adapter disk controller mouse keyboard monitor disk

CPU chip Disk controller reads the sector and performs a direct memory access (DMA) transfer into main memory. register file ALU main memory bus interface I/O bus USB controller graphics adapter disk controller mouse keyboard monitor disk

CPU chip When the DMA transfer completes, the disk controller notifies the CPU with an interrupt (i.e., asserts a special “interrupt” pin on the CPU) register file ALU main memory bus interface I/O bus USB controller graphics adapter disk controller mouse keyboard monitor disk

Storage Trends SRAM DRAM Disk
metric :1980 $/MB 19,200 2, access (ns) SRAM metric :1980 $/MB 8, ,000 access (ns) typical size(MB) ,000 DRAM metric :1980 $/MB ,000 access (ms) typical size(MB) ,000 9,000 9,000 Disk (Culled from back issues of Byte and PC Magazine)

CPU Clock Rates :1980 processor Pent P-III clock rate(MHz) cycle time(ns) 1,

The CPU-Memory Gap The increasing gap between DRAM, disk, and CPU speeds.

Locality Principle of Locality: Locality Example:
Programs tend to reuse data and instructions near those they have used recently, or that were recently referenced themselves. Temporal locality: Recently referenced items are likely to be referenced in the near future. Spatial locality: Items with nearby addresses tend to be referenced close together in time. Locality Example: Data Reference array elements in succession (stride-1 reference pattern): Reference sum each iteration: Instructions Reference instructions in sequence: Cycle through loop repeatedly: sum = 0; for (i = 0; i < n; i++) sum += a[i]; return sum; Spatial locality Temporal locality Spatial locality Temporal locality

Locality Example Claim: Being able to look at code and get a qualitative sense of its locality is a key skill for a professional programmer. Question: Does this function have good locality? int sumarrayrows(int a[M][N]) { int i, j, sum = 0; for (i = 0; i < M; i++) for (j = 0; j < N; j++) sum += a[i][j]; return sum }

Locality Example Question: Does this function have good locality?
int sumarraycols(int a[M][N]) { int i, j, sum = 0; for (j = 0; j < N; j++) for (i = 0; i < M; i++) sum += a[i][j]; return sum }

Locality Example Question: Can you permute the loops so that the function scans the 3-d array a[] with a stride-1 reference pattern (and thus has good spatial locality)? int sumarray3d(int a[M][N][N]) { int i, j, k, sum = 0; for (i = 0; i < M; i++) for (j = 0; j < N; j++) for (k = 0; k < N; k++) sum += a[k][i][j]; return sum }

Memory Hierarchies Some fundamental and enduring properties of hardware and software: Fast storage technologies cost more per byte and have less capacity. The gap between CPU and main memory speed is widening. Well-written programs tend to exhibit good locality. These fundamental properties complement each other beautifully. They suggest an approach for organizing memory and storage systems known as a memory hierarchy.

An Example Memory Hierarchy
Smaller, faster, and costlier (per byte) storage devices L0: registers CPU registers hold words retrieved from L1 cache. L1: on-chip L1 cache (SRAM) L1 cache holds cache lines retrieved from the L2 cache memory. off-chip L2 cache (SRAM) L2: L2 cache holds cache lines retrieved from main memory. main memory (DRAM) L3: Larger, slower, and cheaper (per byte) storage devices Main memory holds disk blocks retrieved from local disks. local secondary storage (local disks) L4: Local disks hold files retrieved from disks on remote network servers. remote secondary storage (distributed file systems, Web servers) L5:

Caches Cache: A smaller, faster storage device that acts as a staging area for a subset of the data in a larger, slower device. Fundamental idea of a memory hierarchy: For each k, the faster, smaller device at level k serves as a cache for the larger, slower device at level k+1. Why do memory hierarchies work? Programs tend to access the data at level k more often than they access the data at level k+1. Thus, the storage at level k+1 can be slower, and thus larger and cheaper per bit. Net effect: A large pool of memory that costs as much as the cheap storage near the bottom, but that serves data to programs at the rate of the fast storage near the top.

Caching in a Memory Hierarchy
8 9 14 3 Smaller, faster, more expensive device at level k caches a subset of the blocks from level k+1 Level k: 4 10 Data is copied between levels in block-sized transfer units 10 4 1 2 3 4 4 5 6 7 Larger, slower, cheaper storage device at level k+1 is partitioned into blocks. Level k+1: 8 9 10 10 11 12 13 14 15

General Caching Concepts
Program needs object d, which is stored in some block b. Cache hit Program finds b in the cache at level k. E.g., block 14. Cache miss b is not at level k, so level k cache must fetch it from level k E.g., block 12. If level k cache is full, then some current block must be replaced (evicted). Which one is the “victim”? Placement policy: where can the new block go? E.g., b mod 4 Replacement policy: which block should be evicted? E.g., LRU Request 14 Request 12 12 14 1 2 3 Level k: 4* 4* 12 9 14 14 3 Request 12 12 4* 1 2 3 Level k+1: 4 4* 5 6 7 8 9 10 11 12 12 13 14 15

General Caching Concepts
Types of cache misses: Cold (compulsary) miss Cold misses occur because the cache is empty. Conflict miss Most caches limit blocks at level k+1 to a small subset (sometimes a singleton) of the block positions at level k. E.g. Block i at level k+1 must be placed in block (i mod 4) at level k+1. Conflict misses occur when the level k cache is large enough, but multiple data objects all map to the same level k block. E.g. Referencing blocks 0, 8, 0, 8, 0, 8, ... would miss every time. Capacity miss Occurs when the set of active cache blocks (working set) is larger than the cache.

Examples of Caching in the Hierarchy
Hardware On-Chip TLB Address translations TLB Web browser 10,000,000 Local disk Web pages Browser cache Web cache Network buffer cache Buffer cache Virtual Memory L2 cache L1 cache Registers Cache Type Parts of files 4-KB page 32-byte block 4-byte word What Cached Web proxy server 1,000,000,000 Remote server disks OS 100 Main memory 1 On-Chip L1 10 Off-Chip L2 AFS/NFS client Hardware+OS Compiler CPU registers Managed By Latency (cycles) Where Cached

Cache Memories CENG331: Introduction to Computer Systems 10th Lecture
Instructor: Erol Sahin Acknowledgement: Most of the slides are adapted from the ones prepared by R.E. Bryant, D.R. O’Hallaron of Carnegie-Mellon Univ.

Overview Topics Generic cache memory organization Direct mapped caches
Set associative caches Impact of caches on performance

Cache Memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory CPU looks first for data in L1, then in L2, then in main memory. Typical bus structure: CPU chip register file ALU L1 cache cache bus system bus memory bus main memory L2 cache bus interface I/O bridge

Inserting an L1 Cache Between the CPU and Main Memory
The tiny, very fast CPU register file has room for four 4-byte words. The transfer unit between the CPU register file and the cache is a 4-byte block. line 0 The small fast L1 cache has room for two 4-word blocks. line 1 The transfer unit between the cache and main memory is a 4-word block (16 bytes). block 10 a b c d ... The big slow main memory has room for many 4-word blocks. block 21 p q r s ... block 30 w x y z ...

General Org of a Cache Memory
1 valid bit per line t tag bits per line B = 2b bytes per cache block Cache is an array of sets. Each set contains one or more lines. Each line holds a block of data. valid tag 1 • • • B–1 E lines per set set 0: • • • valid tag 1 • • • B–1 valid tag 1 • • • B–1 • • • set 1: S = 2s sets valid tag 1 • • • B–1 • • • valid tag 1 • • • B–1 set S-1: • • • valid tag 1 • • • B–1 Cache size: C = B x E x S data bytes

Addressing Caches The word at address A is in the cache if
t bits s bits b bits m-1 v tag 1 • • • B–1 set 0: • • • <tag> <set index> <block offset> v tag 1 • • • B–1 v tag 1 • • • B–1 set 1: • • • v tag 1 • • • B–1 The word at address A is in the cache if the tag bits in one of the <valid> lines in set <set index> match <tag>. The word contents begin at offset <block offset> bytes from the beginning of the block. • • • v tag 1 • • • B–1 set S-1: • • • v tag 1 • • • B–1

Direct-Mapped Cache Simplest kind of cache
Characterized by exactly one line per set. set 0: valid tag cache block E=1 lines per set set 1: valid tag cache block • • • set S-1: valid tag cache block

Accessing Direct-Mapped Caches
Set selection Use the set index bits to determine the set of interest. set 0: valid tag cache block selected set set 1: valid tag cache block • • • t bits s bits b bits set S-1: valid tag cache block m-1 tag set index block offset

Accessing Direct-Mapped Caches
Line matching and word selection Line matching: Find a valid line in the selected set with a matching tag Word selection: Then extract the word =1? (1) The valid bit must be set 1 2 3 4 5 6 7 selected set (i): 1 0110 w0 w1 w2 w3 = ? (2) The tag bits in the cache line must match the tag bits in the address (3) If (1) and (2), then cache hit, and block offset selects starting byte. t bits s bits b bits 0110 i 100 m-1 tag set index block offset

Direct-Mapped Cache Simulation
M=16 byte addresses, B=2 bytes/block, S=4 sets, E=1 entry/set Address trace (reads): 0 [00002], 1 [00012], 13 [11012], 8 [10002], 0 [00002] x t=1 s=2 b=1 xx 1 m[1] m[0] v tag data 0 [00002] (miss) (1) 1 m[1] m[0] v tag data m[13] m[12] 13 [11012] (miss) (3) M[0-1] 1 1 M[12-13] M[0-1] 1 m[9] m[8] v tag data 8 [10002] (miss) (4) 1 m[1] m[0] v tag data m[13] m[12] 0 [00002] (miss) (5) 1 M[12-13] M[8-9] 1 M[12-13] M[0-1]

Why Use Middle Bits as Index?
High-Order Bit Indexing Middle-Order Bit Indexing 4-line Cache 00 0000 0000 01 0001 0001 10 0010 0010 11 0011 0011 0100 0100 High-Order Bit Indexing Adjacent memory lines would map to same cache entry Poor use of spatial locality Middle-Order Bit Indexing Consecutive memory lines map to different cache lines Can hold C-byte region of address space in cache at one time 0101 0101 0110 0110 0111 0111 1000 1000 1001 1001 1010 1010 1011 1011 1100 1100 1101 1101 1110 1110 1111 1111

Set Associative Caches
Characterized by more than one line per set valid tag cache block set 0: E=2 lines per set valid tag cache block valid tag cache block set 1: valid tag cache block • • • valid tag cache block set S-1: valid tag cache block

Accessing Set Associative Caches
Set selection identical to direct-mapped cache valid tag cache block set 0: valid tag cache block valid tag cache block Selected set set 1: valid tag cache block • • • valid tag cache block t bits s bits set S-1: b bits valid tag cache block m-1 tag set index block offset

Accessing Set Associative Caches
Line matching and word selection must compare the tag in each valid line in the selected set. =1? (1) The valid bit must be set. 1 2 3 4 5 6 7 1 1001 selected set (i): = ? (2) The tag bits in one of the cache lines must match the tag bits in the address 1 0110 w0 w1 w2 w3 (3) If (1) and (2), then cache hit, and block offset selects starting byte. t bits s bits b bits 0110 i 100 m-1 tag set index block offset

Multi-Level Caches Options: separate data and instruction caches, or a unified cache Unified L2 Cache Memory Regs L1 d-cache Processor disk L1 i-cache size: speed: $/Mbyte: line size: 200 B 3 ns 8 B 8-64 KB 3 ns 32 B 1-4MB SRAM 6 ns $100/MB 32 B 128 MB DRAM 60 ns $1.50/MB 8 KB 30 GB 8 ms $0.05/MB larger, slower, cheaper

Intel Pentium Cache Hierarchy
Processor Chip L1 Data 1 cycle latency 16 KB 4-way assoc Write-through 32B lines L2 Unified 128KB--2 MB 4-way assoc Write-back Write allocate 32B lines Main Memory Up to 4GB Regs. L1 Instruction 16 KB, 4-way 32B lines

Intel i7 processor Before, Intel Core 2 Duo and Quad processors had just an L1 and L2 cache. i7 features L1, L2, and shared L3 caches. 64K L1 cache (32K Instruction, 32K Data) per core, 1MB of total L2 cache, and 8MB of L3 cache that is shared across all the cores. That means that all Intel Core i7 processors have over 9MB of memory right there on the 45nm processor

Quick Path interconnect
Intel i7 architecture 32 KB L1 inst cache is 4-way set associative 32 KB L1 data cache is 8-way set associative 256 KB L2 unified i+d cache is 8 MB L3 shared cache 16-way set associative all cache lines are 64 bytes in size MESI+F (forward) coherency Core 1 32 KB L1-I 32 KB L1-d 256 KB L2 Core 2 32 KB L1-I 32 KB L1-d 256 KB L2 Core 3 32 KB L1-I 32 KB L1-d 256 KB L2 Core 4 32 KB L1-I 32 KB L1-d 256 KB L2 8 MB shared L3 Integrated Memory Controller Quick Path interconnect

Hits L1 cache hit 4 cycles L2 cache hit 10 cycles L3 cache hit, line unshared ~40 cycles L3 cache hit, shared line in another core ~65 cycles L3 cache hit, modified in another core ~75 cycles Local DRAM ~ cycles Remote L3 cache or remote DRAM ~ cycles

TLB cache 7-entry instruction TLB0, fully associative, maps 2 MB or 4 MB super pages 32-entry data TLB0, 4-way set associative, maps 2 MB or 4 MB super pages 64-entry instruction TLB, 4-way set associative, maps 4 KB pages 64-entry data TLB, 4-way set associative, maps 4 KB pages 512-entry shared second-level TLB, 4-way set associative, maps 4 KB pages

Cache Performance Metrics
Miss Rate Fraction of memory references not found in cache (misses/references) Typical numbers: 3-10% for L1 can be quite small (e.g., < 1%) for L2, depending on size, etc. Hit Time Time to deliver a line in the cache to the processor (includes time to determine whether the line is in the cache) 1 clock cycle for L1 3-8 clock cycles for L2 Miss Penalty Additional time required because of a miss Typically cycles for main memory

Writing Cache Friendly Code
Repeated references to variables are good (temporal locality) Stride-1 reference patterns are good (spatial locality) Examples: cold cache, 4-byte words, 4-word cache blocks int sumarrayrows(int a[M][N]) { int i, j, sum = 0; for (i = 0; i < M; i++) for (j = 0; j < N; j++) sum += a[i][j]; return sum; } int sumarraycols(int a[M][N]) { int i, j, sum = 0; for (j = 0; j < N; j++) for (i = 0; i < M; i++) sum += a[i][j]; return sum; } Miss rate = 1/4 = 25% Miss rate = 100%

The Memory Mountain Read throughput (read bandwidth) Memory mountain
Number of bytes read from memory per second (MB/s) Memory mountain Measured read throughput as a function of spatial and temporal locality. Compact way to characterize memory system performance.

Memory Mountain Test Function
/* The test function */ void test(int elems, int stride) { int i, result = 0; volatile int sink; for (i = 0; i < elems; i += stride) result += data[i]; sink = result; /* So compiler doesn't optimize away the loop */ } /* Run test(elems, stride) and return read throughput (MB/s) */ double run(int size, int stride, double Mhz) { double cycles; int elems = size / sizeof(int); test(elems, stride); /* warm up the cache */ cycles = fcyc2(test, elems, stride, 0); /* call test(elems,stride) */ return (size / stride) / (cycles / Mhz); /* convert cycles to MB/s */

Memory Mountain Main Routine
/* mountain.c - Generate the memory mountain. */ #define MINBYTES (1 << 10) /* Working set size ranges from 1 KB */ #define MAXBYTES (1 << 23) /* ... up to 8 MB */ #define MAXSTRIDE /* Strides range from 1 to 16 */ #define MAXELEMS MAXBYTES/sizeof(int) int data[MAXELEMS]; /* The array we'll be traversing */ int main() { int size; /* Working set size (in bytes) */ int stride; /* Stride (in array elements) */ double Mhz; /* Clock frequency */ init_data(data, MAXELEMS); /* Initialize each element in data to 1 */ Mhz = mhz(0); /* Estimate the clock frequency */ for (size = MAXBYTES; size >= MINBYTES; size >>= 1) { for (stride = 1; stride <= MAXSTRIDE; stride++) printf("%.1f\t", run(size, stride, Mhz)); printf("\n"); } exit(0);

The Memory Mountain

Ridges of Temporal Locality
Slice through the memory mountain with stride=1 illuminates read throughputs of different caches and memory

A Slope of Spatial Locality
Slice through memory mountain with size=256KB shows cache block size.

Matrix Multiplication Example
Major Cache Effects to Consider Total cache size Exploit temporal locality and keep the working set small (e.g., by using blocking) Block size Exploit spatial locality Description: Multiply N x N matrices O(N3) total operations Accesses N reads per source element N values summed per destination but may be able to hold in register /* ijk */ for (i=0; i<n; i++) { for (j=0; j<n; j++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; } Variable sum held in register

Miss Rate Analysis for Matrix Multiply
Assume: Line size = 32B (big enough for 4 64-bit words) Matrix dimension (N) is very large Approximate 1/N as 0.0 Cache is not even big enough to hold multiple rows Analysis Method: Look at access pattern of inner loop A k i B k j i j C

Layout of C Arrays in Memory (review)
C arrays allocated in row-major order each row in contiguous memory locations Stepping through columns in one row: for (i = 0; i < N; i++) sum += a[0][i]; accesses successive elements if block size (B) > 4 bytes, exploit spatial locality compulsory miss rate = 4 bytes / B Stepping through rows in one column: for (i = 0; i < n; i++) sum += a[i][0]; accesses distant elements no spatial locality! compulsory miss rate = 1 (i.e. 100%)

Matrix Multiplication (ijk)
for (i=0; i<n; i++) { for (j=0; j<n; j++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; } Inner loop: (*,j) (i,j) (i,*) A B C Column- wise Fixed Row-wise Misses per Inner Loop Iteration: A B C

Matrix Multiplication (jik)
for (j=0; j<n; j++) { for (i=0; i<n; i++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum } Inner loop: (*,j) (i,j) (i,*) A B C Row-wise Column- wise Fixed Misses per Inner Loop Iteration: A B C

Matrix Multiplication (kij)
for (k=0; k<n; k++) { for (i=0; i<n; i++) { r = a[i][k]; for (j=0; j<n; j++) c[i][j] += r * b[k][j]; } Inner loop: (i,k) (k,*) (i,*) A B C Fixed Row-wise Row-wise Misses per Inner Loop Iteration: A B C

Matrix Multiplication (ikj)
for (i=0; i<n; i++) { for (k=0; k<n; k++) { r = a[i][k]; for (j=0; j<n; j++) c[i][j] += r * b[k][j]; } Inner loop: (i,k) (k,*) (i,*) A B C Row-wise Row-wise Fixed Misses per Inner Loop Iteration: A B C

Matrix Multiplication (jki)
for (j=0; j<n; j++) { for (k=0; k<n; k++) { r = b[k][j]; for (i=0; i<n; i++) c[i][j] += a[i][k] * r; } Inner loop: (*,k) (*,j) (k,j) A B C Column - wise Fixed Column- wise Misses per Inner Loop Iteration: A B C

Matrix Multiplication (kji)
for (k=0; k<n; k++) { for (j=0; j<n; j++) { r = b[k][j]; for (i=0; i<n; i++) c[i][j] += a[i][k] * r; } Inner loop: (*,k) (*,j) (k,j) A B C Column- wise Fixed Column- wise Misses per Inner Loop Iteration: A B C

Summary of Matrix Multiplication
ijk (& jik): 2 loads, 0 stores misses/iter = 1.25 kij (& ikj): 2 loads, 1 store misses/iter = 0.5 jki (& kji): 2 loads, 1 store misses/iter = 2.0 for (i=0; i<n; i++) { for (j=0; j<n; j++) { sum = 0.0; for (k=0; k<n; k++) sum += a[i][k]*b[k][j]; c[i][j] = sum; } for (k=0; k<n; k++) { for (i=0; i<n; i++) { r = a[i][k]; for (j=0; j<n; j++) c[i][j] += r*b[k][j]; } for (j=0; j<n; j++) { for (k=0; k<n; k++) { r = b[k][j]; for (i=0; i<n; i++) c[i][j] += a[i][k] * r; }

Pentium Matrix Multiply Performance
Miss rates are helpful but not perfect predictors. Code scheduling matters, too.

Improving Temporal Locality by Blocking
Example: Blocked matrix multiplication “block” (in this context) does not mean “cache block”. Instead, it mean a sub-block within the matrix. Example: N = 8; sub-block size = 4 A11 A12 A21 A22 B11 B12 B21 B22 C11 C12 C21 C22 = X Key idea: Sub-blocks (i.e., Axy) can be treated just like scalars. C11 = A11B11 + A12B C12 = A11B12 + A12B22 C21 = A21B11 + A22B C22 = A21B12 + A22B22

Blocked Matrix Multiply (bijk)
for (jj=0; jj<n; jj+=bsize) { for (i=0; i<n; i++) for (j=jj; j < min(jj+bsize,n); j++) c[i][j] = 0.0; for (kk=0; kk<n; kk+=bsize) { for (i=0; i<n; i++) { for (j=jj; j < min(jj+bsize,n); j++) { sum = 0.0 for (k=kk; k < min(kk+bsize,n); k++) { sum += a[i][k] * b[k][j]; } c[i][j] += sum;

Blocked Matrix Multiply Analysis
Innermost loop pair multiplies a 1 X bsize sliver of A by a bsize X bsize block of B and accumulates into 1 X bsize sliver of C Loop over i steps through n row slivers of A & C, using same B for (i=0; i<n; i++) { for (j=jj; j < min(jj+bsize,n); j++) { sum = 0.0 for (k=kk; k < min(kk+bsize,n); k++) { sum += a[i][k] * b[k][j]; } c[i][j] += sum; Innermost Loop Pair kk jj jj kk i i A B C Update successive elements of sliver row sliver accessed bsize times block reused n times in succession

Pentium Blocked Matrix Multiply Performance
Blocking (bijk and bikj) improves performance by a factor of two over unblocked versions (ijk and jik) relatively insensitive to array size.

Concluding Observations
Programmer can optimize for cache performance How data structures are organized How data are accessed Nested loop structure Blocking is a general technique All systems favor “cache friendly code” Getting absolute optimum performance is very platform specific Cache sizes, line sizes, associativities, etc. Can get most of the advantage with generic code Keep working set reasonably small (temporal locality) Use small strides (spatial locality)

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