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2. 2 Electronics Beyond Nano-scale CMOS Shekhar Borkar Intel Corp. July 27, 2006

3. 3 Outline Evolution of Electronics to CMOS Evolution of Electronics to CMOS The three tenets The three tenets Technology outlook Technology outlook Challenges Challenges Potential solutions Potential solutions Summary Summary

4. 4 Evolution of Electronics Mechanical Electro-Mechanical Electronic-VT Bipolar NMOS CMOS…….  ? All cross-road technologies show 1.Gain 2.Signal/Noise 3.Scalability Performance Energy Price/Performance

5. 5 The Three Tenets Gain Input Output Energy (1) Signal/ Noise Input Output (2) Scalability, in some shape or form (3)

6. 6 Electro-Mechanical scaling— Relays 1928, Otis Elevator

7. 7 Vacuum Tubes 1930’s 1920’s 1950’s & 60’s

8. 8 Semiconductors The first transistor The first integrated circuit 4004 Pentium® 4

9. 9 Benefits of Scaling

10. 10 Technology Outlook High Volume Manufacturing 20042006200820102012201420162018 Technology Node (nm) 906545322216118 Integration Capacity (BT) 248163264128256 Delay = CV/I scaling 0.7~0.7>0.7 Delay scaling will slow down Energy/Logic Op scaling >0.35>0.5>0.5 Energy scaling will slow down Bulk Planar CMOS High Probability Low Probability Alternate, 3G etc Low Probability High Probability Variability Medium High Very High ILD (K) ~3<3 Reduce slowly towards 2-2.5 Reduce slowly towards 2-2.5 RC Delay 11111111 Metal Layers 6-77-88-9 0.5 to 1 layer per generation

11. 11 Si Substrate Metal Gate High-k Tri-Gate S G D III-V S Carbon Nanotube FET 50 nm 35 nm 30 nm SiGe S/D Strained Silicon SiGe S/D Strained Silicon 90 nm65 nm45 nm32 nm 20042006200820102012+ Technology Generation 20 nm 10 nm 5 nm Nanowire Manufacturing Development Research CMOS Research Continues…

12. 12 CMOS—Cross Road? Cross Road False Alarms 1  Short Channel Effects Device Engineering 0.5  Interconnects More metals, Cu Low K ILD 130 nm SD Leakage Leakage control, avoidance, tolerance 65 nm Gate Leakage Hi-K + Metal Gate 22 nm Lithography EUV, Self assembly ……… < 1.5nm SD Tunneling ?

13. 13 What’s in sight after CMOS? Which technology shows gain? Which technology shows gain? Satisfactory signal to noise ratio? Satisfactory signal to noise ratio? – At room temperature? Scalability in some shape or form? Scalability in some shape or form? –Performance, Energy, Cost Research must continue to find one Research must continue to find one Then it will take 10-15 years to mature Then it will take 10-15 years to mature Until then… Until then… CMOS will continue…

14. 14 …But With Challenges! Heat Flux (W/cm 2 )—Vcc variation Temp Variation & Hot spots Random Dopant Fluctuations 193nm 248nm 365nm LithographyWavelength 65nm 90nm 130nm Generation Gap 45nm 32nm 13nm EUV 180nm Source: Mark Bohr, Intel Sub-wavelength Lithography

15. 15 Yesterday’s Freelance Layout V ss V dd OpOp IpIp V ss V dd OpOp No layout restrictions

16. 16 Transistor Orientation Restrictions V ss V dd OpOp IpIp V ss V dd OpOp Transistor orientation restricted to improve manufacturing control

17. 17 OpOp V ss V dd IpIp V ss V dd OpOp Transistor Width Quantization

18. 18 Today’s Unrestricted Routing

19. 19 Future Metal Restrictions

20. 20 Reliability Soft Error FIT/Chip (Logic & Mem) Time dependent device degradation Burn-in may phase out…? Extreme device variations Wider

21. 21 Implications to Reliability Extreme variations (Static & Dynamic) will result in unreliable components Extreme variations (Static & Dynamic) will result in unreliable components Impossible to design reliable system as we know today Impossible to design reliable system as we know today –Transient errors (Soft Errors) –Gradual errors (Variations) –Time dependent (Degradation) Reliable systems with unreliable components —Resilient  Architectures Reliable systems with unreliable components —Resilient  Architectures

22. 22 Implications to Design & Test Design with regular fabric Design with regular fabric One-time-factory testing will be out One-time-factory testing will be out Burn-in to catch chip infant-mortality will not be practical Burn-in to catch chip infant-mortality will not be practical Test HW will be part of the design Test HW will be part of the design Dynamically self-test, detect errors, reconfigure, & adapt Dynamically self-test, detect errors, reconfigure, & adapt

23. 23 In a Nut-shell… 100 Billion Transistors 100 BT integration capacity Billions unusable (variations) Some will fail over time Yet, deliver high performance in the power & cost envelope Intermittent failures

24. 24 Recipe for Resiliency 1. Detect 2. Isolate 3. Confine 4. Reconfigure 5. Recover & adapt 1. Circuit 2. Firmware 3. Platform 4. Software 5. Application

25. 25 Resiliency with Reconfiguration Dynamic on-chip testing Dynamic on-chip testing Performance profiling Performance profiling Spare hardware Spare hardware Binning strategy Binning strategy Dynamic, fine grain, performance and power management Dynamic, fine grain, performance and power management Coarse-grain redundancy checking Coarse-grain redundancy checking Dynamic error detection & reconfiguration Dynamic error detection & reconfiguration Decommission aging HW, swap with spare Decommission aging HW, swap with spare Dynamically… 1.Self test & detect 2.Isolate errors 3.Confine 4.Reconfigure, and 5.Adapt Dynamically… 1.Self test & detect 2.Isolate errors 3.Confine 4.Reconfigure, and 5.Adapt CC CC CC CC CC CC CC CC

26. 26 Why Bother? G. Moore ISSCC 03 Litho Cost www.icknowledge.com FAB Cost $ per Transistor $ per MIPS

27. 27 Summary Three tenets: Gain, Signal/Noise, Scalability Three tenets: Gain, Signal/Noise, Scalability Nothing on the horizon satisfies them Nothing on the horizon satisfies them Research must continue to find one Research must continue to find one But until then, CMOS rules But until then, CMOS rules Several challenges lay ahead, but when have they not? Several challenges lay ahead, but when have they not?