1. Anthony Gaught Advisors: Dr. In Soo Ahn and Dr. Yufeng Lu Department of Electrical and Computer Engineering Bradley University, Peoria, Illinois May 7, 2013 1

2.  Motivation  Project Goals  Introduction to QPSK  System Block Diagram  Design Methodology  Simulation Results  Hardware Results  Conclusions  References 2

3.  In cellular systems, different data rates are achieved by adjusting modulation and channel coding schemes. A reconfigurable system can meet the ever-increasing demands and reduce the cost of system.  Quadrature Phase Shift Keying (QPSK) is one of the modulation methods adopted in various wireless communication standards.  Different design tools are available to design and implement communication systems. Each has its own advantages and disadvantages. 3

4.  Design a complete QPSK communication system on Field Programmable Gate Arrays(FPGAs) using hardware description language (HDL).  Implement a carrier recovery circuit and a digital phase locked loop to resolve carrier offset in the receiver.  Design and verify the communication system in an efficient way.  Construct the system with hardware-efficient modules which can be reusable and expandable with additional features in the future. 4

5.  s(t) = I(t)cos(2πf c t) – Q(t)sin(2πf c t) 5  Each symbol represents two bits of data.  I and Q bits are determined based on the phase of the received symbol.

6.  A small frequency offset is present between the transmitter and receiver.  Coherent detection is achieved by using a phase locked loop (PLL).  A direct digital synthesizer creates coherent sine and cosine carriers. 6  Carrier signals from the transmitter and receiver need to be synchronized in order to correctly demodulate the received data.

7. 7  I hat (n) and Q hat (n) are the outputs from decimators.  I(n) and Q(n) are estimated hard-decoded data.  Φ is the phase error.  Phase error is used to adjust the frequency and phase of the local oscillator.

8. 8  PI control provides a means to control bandwidth and dampening factor.  By optimizing K p and K i fast locking time and reduced jitter can be achieved.  Bandwidth is chosen first and other parameters are derived using the equations to the left.

9.  Static phase error can occur at integer multiples of 90 degrees  Four possible states as seen on the constellation grid  Can be corrected by differential coding or transmitting a known sequence to synchronize the system 9

10.  Raised cosine filter  Reduces inter-symbol interference (ISI)  Improves bandwidth 10

11. 11  System clock frequency50 MHz50 MHz  Carrier Frequency12.5 MHz184 KHz  Symbol Rate6.25 Msps91.9 Ksps  Data Rate12.5 Mbps184 Kbps  Maximum Carrier Offset1 KHz14.7 Hz Specification one FPGA two FPGAs Specification one FPGA two FPGAs

12.  The QPSK signal, s(t), includes in-phase component, I(t), and quadrature component, Q(t).  r(t) = s(t) + n(t) where n(t) is noise. 12

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14.  VHDL simulation results plotted are against the SIMULINK model results using MATLAB.  Fixed point representation is used throughout the HDL design. 14

15.  Data type: FIX 12_11 15

16.  Data type: FIX 12_11 16

17.  Data type: FIX 12_11 17

18.  Data type: FIX 16_15 18

19.  Error on Ihat and Qhat due to fixed point representation and truncation  I hat Mean square error = 5.44 x 10 -5  Q hat Mean square error = 5.68 x 10 -5 19

20.  Data type: FIX 32_31 20 Frequency offset = 500 Hz Mean square error = 1.86 x 10 -11

21.  Data type: FIX 2_0 21

22.  The design is implemented on Spartan 3E Boards.  P-mod DA2 and P-mod AD1 modules are used transmit the signal between FPGAs.  Signals of interest are displayed on an oscilloscope. 22

23.  Constellation plot for the transmitted data 23

24.  Constellation plot for the received data  Transmitter and receiver on the same FPGA  s(n) is an internal digital signal. 24 Frequency offset 1 KHz

25. 25 Frequency offset 14.7 Hz  Constellation plot for the received data  Transmitter and receiver on separate FPGAs  s(t) is an external analog signal.

26.  Data type: FIX 2_0 26 (From top down)  Transmitted data  Received data on the same FPGA  Received data on separate FPGAs

27. 27  It  Qt  I r  Q r (From top down)

28. 28 (From top down)  It  Qt  I r  Q r

29.  Correct for phase ambiguity  Wireless transmission of the modulated signal  Implementation of other modulation schemes such as higher order PSK, quadrature amplitude modulation (QAM) or others 29

30.  In this project, a reconfigurable QPSK communication system has been designed using HDL.  The system has been implemented on low-cost Xilinx Spartan3E boards.  An efficient verification flow has been applied to the design.  Carrier recovery circuit and digital phase locked loop are used to resolve carrier offset which is essential for decoding of the transmitted data. 30

31.  Anton Rodriguez, and Michael Mensinger Jr., “Software-defined Radio using Xilinx”, Senior Project Report, Department of Electrical and Computer Engineering, Bradley University, Peoria Illinois, May 2011.  Anthony Gaught, Alexander Norton, and Christopher Brady., “FPGA-based 16 QAM communication system”, Digilent design contest Report, Department of Electrical and Computer Engineering, Bradley University, Peoria Illinois, April 2012.  Leon Couch, “Digital and analog communication systems”, 8th edition, Boston: Pearson, 2013. 31

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