1. COMP541 Combinational Logic - I
Montek Singh
Mon, Jan 12, 2015

2. Today Basics of digital logic (review) Basic gates Combinational logic
Various representations
Boolean algebra
Truth tables
Karnaugh Maps (“K-Maps”)
Circuit schematic diagrams
Hardware Description Languages (HDL)

3. Binary Logic Binary variables
Can be 0 or 1 (True or False, low or high)
Variables named with single letters in examples
Really use words when designing circuits

4. Logic Gates Perform logic functions: Single-input: Two-input:
inversion (NOT), AND, OR, NAND, NOR, etc.
Single-input:
NOT gate
buffer (non-inverting)
Two-input:
AND, OR, XOR, NAND, NOR, XNOR
Multiple-input
Most 2-input gates also have multi-input flavors

5. Single-Input Logic Gates

6. Two-Input Logic Gates

7. More Two-Input Logic Gates

8. More Two-Input Logic Gates

9. Multiple-Input Logic Gates

10. Multiple-Input Logic Gates

11. NAND is Universal
Can express any Boolean Function

12. Using NAND as Invert-OR
DeMorgan’s Law:
Also reverse inverter diagram for clarity

13. NOR Also Universal
Dual of NAND: also can express any Boolean func

14. Representation: Schematic
“Schematic” is short for “schematic diagram”
Simply means a drawing showing gates (or more complex modules) and wire connections
More complex modules are usually shown as black boxes

15. Representation: Boolean Algebra
More on this next class

16. Representation: Truth Table
2n rows: where n is # of variables

17. Schematic Diagrams
Can you design a Pentium or a graphics chip that way?
Well, yes, but diagrams are overly complex and hard to enter
These days people represent the same thing with text
You can call it “code,” but it is not software!
More precisely, it is a textual “description”

18. Hardware Description Languages
Main ones are Verilog and VHDL
Others: Abel, SystemC, Handel
Origins as testing languages
To generate sets of input values
Levels of use from very detailed to more abstract descriptions of hardware

19. Design w/ HDL Two leading HDLs:
Verilog
developed in 1984 by Gateway Design Automation
became an IEEE standard (1364) in 1995
VHDL
Developed in 1981 by the Department of Defense
Became an IEEE standard (1076) in 1987
Most (all?) commercial designs built using HDLs
We will use Verilog

20. Uses of HDL Simulation Synthesis IMPORTANT:
Defines input values applied to the circuit
Outputs checked for correctness
Millions of dollars saved by debugging in simulation instead of hardware
Synthesis
Transforms HDL code into a circuit-level implementation
HDL is transformed into a “netlist”
“Netlist” = a list of gates and the wires connecting them
Just a textual description instead of drawing
IMPORTANT:
When describing circuits using an HDL, it is critical to think of the hardware the code should produce.

21. Verilog Module Code always organized in modules
Represent a logic “box”
With inputs and outputs

22. Example
module example(input a, b, c, output y); *** HDL DESCRIPTION HERE *** endmodule

23. Levels of Verilog Several different levels (or “views”)
Mainly two types: Structural or Behavioral
Structural: Describe the physical structure of the hardware
Typically, gates/modules and wires that connect them
Behavioral: Describes the algorithmic behavior of the hardware
E.g., Output X = Y + Z

24. Example 1 Output is 1 when input < 011
Figure (b) is called a “Karnaugh Map” (or “K-Map”)
graphical representation of truth table: n-dimensional “cube”
Figure (c) is a “sum-of-products” implementation
AND-OR, implemented as NAND-NAND

25. Structural Verilog Explicit description of gates and connections
Textual form of schematic
Specifying netlist
netlist = gates/modules and their wire connections

26. Example 1 in Structural Verilog
module example_1(X,Y,Z,F);
input X;
input Y;
input Z;
output F;
//wire X_n, Y_n, Z_n, f1, f2;
not
g0(X_n, X),
g1(Y_n, Y),
g2(Z_n, Z);
nand
g3(f1, X_n, Y_n),
g4(f2, X_n, Z_n),
g5(F, f1, f2);
endmodule
Newer syntax:
module example_1(
input X,
input Y,
input Z,
output F );
Can also be:
input X, Y, Z;
output F;

27. Slight Variation – Gates not named
module example_1_c(X,Y,Z,F);
input X;
input Y;
input Z;
output F;
not(X_n, X);
not(Y_n, Y);
not(Z_n, Z);
nand(f1, X_n, Y_n);
nand(f2, X_n, Z_n);
nand(F, f1, f2);
endmodule
Observe:
each gate is declared using a separate “not” or “nand” declaration
gate instances are not named

28. Explanation Each of these gates is an instance
Like object vs class
In first example, they had names
not g0(X_n, X),
In second example, no name
not(X_n, X);
Why can naming an instance be useful?

29. Gates Standard set of gates available and, or, not nand, nor xor, xnor
buf

30. Dataflow Description (Behavioral)
module example_1_b(X,Y,Z,F);
input X;
input Y;
input Z;
output F;
assign F = (~X & ~Y) | (~X & ~Z);
endmodule
Basically a logical expression
No explicit gates

31. Conditional Expressions
Useful for:
describing multiplexers
combinational logic in an if-then-else style
module example_1_c(input [2:0] A,
output F);
assign F = (A > 3’b011) ? 0 : 1;
endmodule
Notice
alternate
specification

32. Abstraction
Using the digital abstraction we have been thinking of the inputs and outputs as
True or False
1 or 0
What are they really?

33. Logic Levels Define discrete voltages to represent 1 and 0
For example, we could define:
0 to be ground or 0 volts
1 to be VDD or 5 volts
What about 4.99 volts? Is that a 0 or a 1?
What about 3.2 volts?

34. Logic Levels Define a range of voltages to represent 1 and 0
Define different ranges for outputs and inputs to allow for noise in the system
What is noise?

35. What is Noise? Anything that degrades the signal
E.g., resistance, power supply noise, coupling to neighboring wires, etc.
Example: a gate (driver) could output a 5 volt signal but, because of resistance in a long wire, the signal could arrive at the receiver with a degraded value, for example, 4.5 volts

36. The Static Discipline
Given logically valid inputs, every circuit element must produce logically valid outputs
Discipline ourselves to use limited ranges of voltages to represent discrete values

37. Logic Levels
NMH = VOH – VIH
NML = VIL – VOL

38. DC Transfer Characteristics
(See textbook for characteristics of an inverter)
Ideal Buffer: Real Buffer:
NMH = NML = VDD/2
NMH , NML < VDD/2

39. VDD Scaling Chips in the 1970s and 1980s were designed using VDD = 5 V
As technology improved, VDD dropped
Avoid frying tiny transistors
Save power
3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, …

40. Logic Family Examples Logic Family VDD VIL VIH VOL VOH TTL
5 ( )
0.8
2.0
0.4
2.4
CMOS
5 ( )
1.35
3.15
0.33
3.84
LVTTL
3.3 ( )
LVCMOS
0.9
1.8
0.36
2.7

41. Next Class
Boolean Algebra
Synthesis of combinational logic