1. Eonic BV Laurens Bierens, chief technology officer laurens.bierens@eonic.com Digitally Mastering The Spectrum From Deep Space to Deep Sea Digitally Mastering The Spectrum Reconfigurable firmware for high- end data flow processing systems

2. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems2 Outline Objective of the presentation Eonic BV : the company FFT data flow processing Connectivity FPGA : Switch Fabric SAR: an FFT data flow processing case SAR algorithm requirement analysis Example system architecture and components Conclusions

3. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems3 Objective of the presentation

4. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems4 Objective of the presentation Introduce the concept of (FFT) data flow processing Elaborate on the key reconfigurable firmware item in the data flow driven application : the connectivity FPGA Show the necessity of reconfigurable firmware in high-end application fields Work out a case example : SAR processing, a high-end data flow driven application

5. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems5 Eonic BV : the company

6. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems6 Eonic BV : the company Result of merger in May 2003 between : Eonic Solutions GmbH, focusing on the Atlas Universal DSP Computer doubleBW Systems BV, spin-off of TNO Focus : „Digitally Mastering the Spectrum“ Products : PowerFFT : fastest FFT-centric floating point DSP in the world Digitizing Systems : 1.0 to 1.5 Gsps (8bit) 105 Msps (14bit) Data recording at up to 180 Mb/sec/channel to RAID disks Atlas : scalable multi-DSP system for back-end processing and system architecture based on PowerFFT, ADI TS101S, ADI 21160, Altera Stratix LVDS point-to-point communication links Supported by Real-Time System Software

7. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems7 What markets do we address? Medical Imaging Telecoms Digital Radio Software Defined Radio DefenseAerospace Embedded DSP Computing

8. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems8 High-end applications Radar & SAR Software Defined Radio COMINT & ELINT Medical Imaging Visual inspection Instrumentation Sonar & active noise control DNA sequencing

9. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems9 Eonic‘s Total Value Proposition Digitizing Front-end computing Back-end computing Signal User / info Eonic covers from front-end to back-end

10. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems10 FFT data flow processing

11. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems11 FFT applications Estimated that 30 to 50 % of all clock cycles in high-end DSP are used for nothing else than calculating an FFT Simplest applications : calculate frequency power spectrum analyse signal in its frequency components recreate signal from its frequency components Derived : correlation, (de)volution beam forming (far field) radar, SAR (image forming radar) communication intelligence,... pattern matching : visual inspection, object tracking, DNA sequencin image manipulation (e.g. image rotation)...

12. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems12 Requirements for embedded FFT engine Act as co-processor for FFT based algorithms in programmable environments Perform FFT based processing in the front-or back-end datastream Perform user controlled multidimensional FFT algorithms in a scaleable way Integrate easily in embedded environments Allow bursty and asynchronous data sources and sinks Allow multiple data input and output formats

13. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems13 PowerFFT processor World’s Fastest Stand-Alone FFT Processor 1K complex floating point FFT in 10  sec What‘s an FFT ? Transforms time-domain signal into frequency domain and vise-versa Basis for many derived algorithms Most DSP algorithms are defined in frequency domain

14. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems14 PowerFFT features / benefits Sustained 1K complex FFT in 10 microsec, incl. windowing (5.7 GFLOPS on a single chip!) Additional I/O ports for 4 SDRAM bank extension: long FFTs, FFT based multi-dimensional algorithms overlapped algorithms and (double buffered) corner turn Programmable Address Generator FPGA: cost-effective memory use (SDRAM vs SRAM) easy upgrades to larger memories specialized memory use (space / mil applications) Extensive data format support: parallel and sequential I&Q IEEE floating point, integer 32/16 sign inv. int. 32/16, 2×24+9 / 2×16+8 hybrid f.p.

15. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems15 Technical Data 100 MHz I/O clock, 128 MHz internal clock, 3.3/1.8 V Power dissipation : max. 2 W, typically 1W Manufactured in 0.18 µm standard CMOS Data types : 32bit IEEE floating point, 32bit, 16bit Applications Radar, SAR, ultrasound, seismic processing, software defined radio, COMINT, ELINT, EW, image processing, beamforming, pattern matching, DNA sequencing,... 1W 1W in operation  suitable suitable for embedded systems PowerFFT characteristics

16. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems16 PowerFFT : a true FFT data flow processor PowerFFT is first in new class of programmable DATA FLOW PROCESSOR Best system performance by co-design with FPGA and DSP for general purpose applications and higher system- level efficiency Data flow processor architecture better adapted to DSP algorithms than classical „von-Neumann“ DSP PowerFFT delivers : fastest 1K Complex FFT sustained performance at 100 Msps programmable low power consumption : 1 W resulting in small system cost DSP (clusters) and FPGA (macro‘s) can also be described as data flow processors, dependent on the application

17. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems17 The connectivity FPGA : Switch Fabrics

18. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems18 Connectivity : the key in data flow processing A massive data flow processing exploits a «network» of data flow processing nodes System performance grows linearly with size Every data flow processor node contributes with its own communication links, its own RAM, its own logic-rich FPGA, and its own I/O capabilities Application re-maps easily from one to many nodes From single data flow processor node...... to a network of data flow processing nodes...... To a complete Atlas™ system

19. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems19 Connectivity FPGA : Switch Fabric Connectivity is guaranteed by using high speed Switch Fabrics with very fast reconfigurability (5 - 10 clock cycles) Two or more controllers are then attached to this Switch Fabric Controllers are either “sinks”, “sources”, or “processes” Examples are outputs, inputs, a multiplier, an FFT (ADC, DSPs, PowerFFT) Controllers are essentially simple autonomous processors - we try to process the data flow in real time We basically have a simple, very high speed distributed computing network, one that can usually fit within one FPGA It is a flexible and efficient means of bulk processing

20. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems20 Switch Fabric PFFT Input Output ADC DSP Memory Controllers Local PCI Operation A Operation B Example data flow module : connectivity

21. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems21 One command line … sets required controllers and Switch Fabric Switch Fabric PFFT Input Output ADC DSP Memory Local PCI Setting up a configuration

22. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems22 Subsequent command lines can start immediately if its required controllers are free Switch Fabric PFFT Input Output ADC DSP Memory Local PCI Setting up the next configuration

23. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems23 All sequencing is performed by the module’s own sequencer. Switch Fabric PFFT Input Output ADC DSP Memory Local PCI Instruction Sequencer Sequencing the data flows

24. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems24 Data flow programming concepts To best serve the programming of data flow processors we require a new approach: We need to explicitly state on which sink and source controller our data resides… …and via which processes to flow Eonic’s data flow compiler concept : a means for optimum connectivity There is no need for the flexibility of a normal DSP therefore a new and more efficient means of compiling data flow instructions is required The compiler is capable of being modified rapidly to match new hardware configurations Currently embedded in the PowerFFT SDE, porting to generic data flow processors is ongoing

25. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems25 SAR: an FFT data flow processing case

26. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems26 What is SAR? Synthetic Aperture Radar (SAR) is a side looking imaging radar mounted on an aircraft A SAR transmits radar pulses and receives the reflections of the ground An image of the illuminated surface of the Earth can be generated by FFT processing the radar data in 2 directions: range (the “look” direction), and azimuth (the “flight” direction) SAR processing is characterized by: Data streams sampled at very high sampling rates Enormous (FFT) processing requirements, up to TerraFLOPS Huge multi-dimensional data sets, >> 10k X 10k samples Multi-dimensional FFT processing “on the fly” in the data flow Eonic data flow processing technology and concepts are extremely applicable in SAR processing

27. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems27 RAMSES multi-frequency SAR from ONERA Transall C160 RAMSES platform RAMSES Ku-band SAR image RAMSES is a multi-frequency SAR system operated by ONERA, the French’ leading aerospace establishment

28. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems28 RAMSES Pre-Processing Unit (RPPU) Eonic developed the RAMSES Pre-Processing Unit (RPPU), a high-end real-time SAR data acquisition, processing and storage system 4 x 1.5 Gsps (8bit) channel, 360 MBytes/sec to raid-0 disk Prefilter up to 1.5 Gsps, multi-channel sync 8 x 105 Msps (14bit) + post processing (DSP, PowerFFT, FPGA)

29. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems29 General system concept Switch Network Digital Front-End RF Receiver Digital Analysis Storage Off-Line Computer Operator

30. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems30 SAR algorithm requirements analysis

31. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems31 Range compression

32. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems32 Exploit parallelism in azimuth compression DSP cluster 1 DSP cluster 2 DSP cluster 3 DSP cluster 4

33. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems33 Algorithm decomposition: processes

34. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems34 Mapping on data flow processor clusters ProcessesCluster# DigitizingDigitizer1 Range CompressionPowerFFT1 1 st Order Motion CompTigerSHARC1 Corner Turn Azimuth Compression TigerSHARCN 2 nd Order Motion Comp 2D FFTPowerFFTN Slant-to-Ground Conv Image constructionTigerSHARC1

35. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems35 Example system architecture and components

36. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems36 System architecture

37. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems37 Atlas 6U dual ADC CompactPCI Under Development

38. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems38 Atlas 6U PowerFFT / 4xTS101S CompactPCI Under Development

39. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems39 Atlas 6U 8xTS101S CompactPCI Under Development

40. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems40 PowerFFT Connectivity FPGA

41. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems41 TigerSHARC Connectivity FPGA

42. 16 October 2003Reconfigurable firwmware for high-end data flow processing systems42 True data flow processors have A high speed switch-fabric at their heart Paths within the switch-fabric that can reconfigure extremely quickly (5-10 clock cycles) An instruction sequencer and distributor that issues the correct instructions to each controller Two or more controllers attached to switch-fabric Controllers are either a “process”, “sink”, “source”, or “both sink and source” Controllers include I/O, memory addressing (often multiple banks), arithmetic logic units, duplicators, data compressors, FFTs, data generators, multiplexers, etc, etc True concurrency: operations (command lines) using different controllers can take place at the same time (no time-slicing) Eonic truly applies its data flow processors in high-end FFT driven stream based DSP architectures Case example shown in typical high-end data flow application: SAR data acquisition, processing and storage PowerFFT, (TigerSharc) DSP (clusters), FPGA macros, can all considered as data flow processors in this application Conclusions