1. Module 4: Metrics & Methodology Topic 2: Signal Quality
OGI EE564
Howard Heck
© H. Heck 2008
Section 4.2

2. Where Are We? Introduction Transmission Line Basics Analysis Tools
Metrics & Methodology
Synchronous Timing
Signal Quality
Source Synchronous Timing
Recovered Clock Timing
Design Methodology
Advanced Transmission Lines
Multi-Gb/s Signaling
Special Topics
© H. Heck 2008
Section 4.2

3. Contents Introduction Receiver Function Receiver Requirements
Signal Quality Metrics
Ringback
Overshoot
Settling Time
Summary
References
© H. Heck 2008
Section 4.2

4. Introduction What does “signal quality” (a.k.a. signal integrity mean?
Here’s an ideal digital signal
Here’s a realistic inter-chip signal
Receiver
Time [ns]
Voltage [V]
Driver
When is it safe to “latch” the data value at the receiver?
Signal quality provides metrics to assess what is good enough to insure accurate switching.
To establish the metrics, we’ll start by looking at the characteristics of receivers for digital signals.
© H. Heck 2008
Section 4.2

5. Receivers Example receiver Receivers rectify input signals
out
clk TO
CORE in
out
clk
Example transfer characteristic V in CC SS
out
Slope = -1 V
OH,min
Die Pad
ESD
Protection
Input
Buffer
Flip-flop
Core
Example receiver
Slope = -1 V
OL,max V
IL,max V
IH,min V
thresh
© H. Heck 2008
Section 4.2

6. Receiver Operating Requirements
Overdrive: Need to drive the input signal beyond the logic threshold to insure reliable and fast response from the receiver.
Stability: Once the signal crosses the threshold, it must stay beyond the threshold. Otherwise we could latch the wrong value.
Limited stress: Repeatedly driving the signal beyond the rails can overstress the ESD diodes and cause reliability problems.
© H. Heck 2008
Section 4.2

7. Signal Quality Metrics
What metrics do we use to insure that signals allow reliable switching?
Overdrive can be handled by specifying the VIL,max and VIH,min for the receiver.
Stability is handled by specifying the amount of ringback that is allowed.
Stress is limited by specifying the amount of overshoot or undershoot that is allowed.
© H. Heck 2008
Section 4.2

8. Metrics Illustrated Settling Limit Overshoot VTT Ringback Vref
VOL
VSS
Undershoot
Settling Limit
© H. Heck 2008
Section 4.2

9. Ringback
VTT
Vref
VOL
VSS
Settling Limit
Ringback
Overshoot
Undershoot
Ringback is the minimum (maximum) voltage to which a signal rebounds on the rising (falling) edge.
Often follows an overshoot or undershoot.
© H. Heck 2008
Section 4.2

10. Overshoot/Undershoot
VTT
Vref
VOL
VSS
Settling Limit
Ringback
Overshoot
Undershoot
Overshoot (or undershoot for falling transitions) is the amount by which the signal’s voltage level beyond the supply “rails”.
Typical overshoot limits are set at one diode drop above the high rail and one diode drop below the low rail.
© H. Heck 2008
Section 4.2

11. Settling Time
VTT
Vref
VOL
VSS
Settling Limit
Ringback
Overshoot
Undershoot
Settling time is a measurement of oscillations on the waveform (usually caused by reflections on the transmission line traces).
Measures the amount of time required for oscillations to dampen to a level that will minimize the impact to the next transition.
© H. Heck 2008
Section 4.2

12. More Settling Time
A historical rule is that oscillations should dampen to within ±10% of the signal swing before the next cycle begins.
If ±10% is not met, simulate multiple cycles (& bit patterns) to make sure that flight times account for settling effects.
Example: 266 MT/s AGP-4X
-0.5
0.0
0.5
1.0
1.5
2.0
Voltage [V]
7.5
15.0
22.5
time [ns]
3.55
3.63
3.71
3.77
3.77
We’ll come back to this in a later section.
© H. Heck 2008
Section 4.2

13. Summary
At speeds of 250 MHz and higher, signal integrity metrics become very important for characterizing buses.
Signals must be settled to their quiescent (static) values before the next transition to avoid cycle-cycle timing uncertainties that eat into the timing budget.
Almost no overshoot or ringback can be tolerated.
© H. Heck 2008
Section 4.2

14. References
S. Hall, G. Hall, and J. McCall, High Speed Digital System Design, John Wiley & Sons, Inc. (Wiley Interscience), 2000, 1st edition.
H.B.Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison Wesley, 1990.
H. Johnson and M. Graham, High Speed Digital Design: A Handbook of Black Magic, PTR Prentice Hall, 1993.
“Transmission Line Effects in PCB Applications,” Motorola Application Note AN1051, 1990.
“Line Driving and System Design,” National Semiconductor Application Note AN-991, April 1995.
K.M. True, “Data Transmission Lines and Their Characteristics,” National Semiconductor Application Note AN-806, February 1996.
W.R. Blood, MECL System Design Handbook, Motorola, Inc., 4th edition, 1988.
© H. Heck 2008
Section 4.2