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Xilinx Programmable Logic Development Systems Foundation ISE version 3
Xilinx most recent development systems offering - version 3.1i - includes a brand new, next generation design environment that delivers the benefits of HDL design to Programmable Logic Designers.
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Foundation ISE An Integrated Synthesis Environment
Complete HDL centric design environment ISE includes Xilinx world-class implementation tools Internet-Enabled project management environment HDL design and synthesis tools HDL testbench and simulation tools Foundation ISE is a complete, HDL centric design environment that delivers world class implementation tools from Xilinx, and internet enabled project management environment, HDL design entry and synthesis tools and HDL testbench and simulation tools via the latest model for 3rd partner alliances - the ALLSTAR program.
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World Class Implementation Tools
The industry’s fastest runtimes 2 to 10X faster than the competition The industry’s highest performance 15 to 25% faster clock rates than the competition The industry’s leading devices V2600E and V3200E, V405EM and V812EM, 2S200, Virtex-II The industry’s most powerful design flows Fast and efficient design methodologies for up to 10 million gates The industry’s most productive partnerships Partners with over 30 of the industry’s most successful companies Logic Designer’s around the world have told us that Xilinx design environments are “Award Winning”. The reasons they state include the following: Their design completes the Places and Routes fastest when run in the Xilinx design environment. Their Design’s achieve the Highest Performance when using Xilinx development systems and devices. Xilinx development systems support the industry’s largest and fastest devices. Xilinx Design Flows provide the most powerful capabilities Xilinx Partnerships with EDA vendors like Exemplar, Synopsys, Synplicity consistently deliver better integration and more effective design flows. The next few foils will go into more detail on each of these award winning capabilities.
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The Industry’s Fastest Runtimes Deliver the Fastest Time To Market
Ultrafast place and route runtimes XCV100: 3-5 minutes (100,000 system gates) XCV1000: minutes (1 million system gates!) Real PCI design 64/66 in XCV300: ~ 5 minutes Consumes ~ 12% of XCV300 BG432 Even faster than our previous release From 10% to 100% for < 1 million gates From 2X to 10X for > 1 million gates Xilinx delivers the industry’s fastest FPGA place and route times when targeting our leading Virtex Series and Spartan II family of devices. When targeting any of these industry leading technology’s, Xilinx has the fastest place and route times - either timing driven or non-timing driven. Examples of some real world design runtimes that we are seeing when running our customer’s designs in-house include 100,000 system gate V100s, with average non-timing driven runtimes of 3 to 5 minutes, and compile times that can be as fast as 1 minute. For customers using our higher density devices, you will be pleased to know that on average we place and route customer designs using this 1 Million System gate device in 30 to 45 minutes. For a real world example, how about our industry best 64 bit, 66 MHz PCI design with place and route times when targeting a XCV300 of around 5 minutes! This specific example included only a very simple interface to verify the proper operation of the PCI core and in total used only 14% of the XCV300. As such, the place and route for a real customer’s design will take longer. If you are currently using our v2.1i tools, you will be pleased to know that medium density design runtimes have been cut in half (again), and high density designs can be completed in as fast as one tenth the time it used to take.
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The Industry’s Best Performance Accelerates Our Customer’s Success
Clock speeds >160 MHz when targeting Virtex-E I/O performance >622 MB per second (mbps) when targeting Virtex-E For existing designs, performance will increase by 10% to 15% from place & route algorithm improvements Approximately a speed grade For Virtex, Virtex-E, Spartan-II devices only Xilinx also delivers the industry’s fastest clock speeds and I/O timing. For customers using our super-fast Virtex E family of devices, clock speeds in excess of 160 MHz are attainable using interactive design flows. Likewise, Xilinx also has reference designs where I/O performance of up to 622 Mbps can be achieved. Of course, not everyone’s design has such stringent timing requirements, or are ideally coded enabling such high performance. For these mainstream designs, Xilinx ability to achieve higher performance also provide great benefits as our customers are able to meet their performance targets using slower less expensive speed grades than the competition. To make it easy to do so, Xilinx provides the industry’s most powerful timing specification language, and easy to use GUIs to simplify the definition of your designs timing requirements, and its analysis once the design is completed. For customers using the v2.1i development system in the creation of any Virtex Series device, or a device from the Spartan II Family, on average their design’s performance should increase by 10 % (or about a speed grade). To be certain, your mileage may vary, as these improvements are design and constraint dependent. However, the average performance for our suite of recently contributed customer benchmark designs improved by 10%, with many increasing by as much as to 15 %.
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The Industry’s Leading Devices
Device Technology Extending the lead with Virtex-E V2600E and V3200E Unequalled memory and logic with the Extended Memory (EM) family V405EM and V812EM Awesome value for high-volume applications The new Spartan-II family 2S200 device Reinventing the FPGA, again with Virtex-II Xilinx Development Systems always provide timely support for the design of our latest device families. The 3.1i software release provides “shrink-wrapped” support for the industry’s largest devices from the Virtex E and Virtex Extended Memory families, and the largest Spartan II device - the 2S200, cost optimized for high-volume applications. For customers requiring access to the leading edge devices that Xilinx will begin shipping at the end of this year, the 3.1i release contains support for the recently announced Virtex II family. If you are interested in designing with these new devices, speak with me after the presentation so I can better explain the Virtex II “early adopter” program.
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The Industry’s Most Powerful Design Flows
Incremental synthesis / layout with high-level floorplanning Efficient methodology for teams using modular design Advanced debug capabilities using ChipScope ILA Seamless Integration with Xilinx EDA ALLSTAR products Many customers have standardized on using Xilinx devices because of the leading edge design methodologies that the Xilinx Development Systems support. While the 3.1i tools are packed with new features, some of the most exciting innovations relate to the improved design flows that it enables. Today I will describe the following exciting new capabilities 3.1i supports - Incremental Design, including Synthesis and Layout, Modular Design, Integrated Logic Analysis and a wonderful convenience - Simple HDL Source Archiving. It is important to note that the version 3 tools have been built to support on-going design flow innovations throughout the year, and as such Xilinx will introduce even more enhancements as part of our quarterly software updates that are due to be released late summer, Fall and during the Winter of 2001!
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Incremental Synthesis through High-Level Floorplanning
Industry First Accelerates your time-to- market Unchanged hierarchical blocks easily guided Preserves timing for blocks unaffected by HDL design changes Accelerates timing closure for complete design Top Level HDL PCI uProcessor USB Ctrl Floorplan defines layout area of each HDL blocks logic The stability and robustness of the Xilinx development systems have enabled Xilinx to be the first FPGA vendor to support an incremental design methodology for all of its leading FPGAs. What makes it work is our Hierarchical floorplanning capability. What is really exciting is that this incremental design flow has been created specifically to work for HDL design flows. And what’s best is that the same incremental design methodology works with Exemplar, Synopsys and Synplicity - so no matter who’s synthesis tools you are using, your design flow has just gotten more efficient. High-Level Floorplanning coupled with Incremental Synthesis accelerates your time to market by isolating the synthesis, optimization, placement and routing design task to only the area of your design that has changed. By preserving the remainder of your design, we can increase your design efficiency AND PERHAPS EVEN MORE IMPORTANTLY - reduce the amount of logic that you need verify when you take your next design revision out to the lab! You see, our incremental design flow preserves the timing of the unchanged portions of your design as well. The Xilinx high-level floorplanner also helps improve the quality of results our synthesis partners obtain by enabling synthesis tools like Synplicity’s Amplify (RTL floorplanner) establish more accurate “and aggressive” timing estimates for the interconnect delays within each floorplanned hierarchical block.
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How High-Level Floorplanning Works
Incremental synthesis limits the name and logic changes to a single block instead of an entire design Top Block A Block B Block C Block D Xilinx high-level floorplanning isolates the place and route task to the area of the design that has changed and maintains timing of unchanged hierarchical blocks This image demonstrates just how High-Level Floorplanning works with incremental synthesis. With High-level floorplanning and incremental synthesis, the place and route tools only have to work on the area of the design that has changed. That’s because the unchanged portions of the design are readily guided as their names, logic structures and routing hasn’t changed from the previous version of the completed design. For areas of the design that have changed, the task of placing and routing the logic is relatively simple as the area to be used in re-implementing the block of logic has been floorplanned to an area EXCLUSIVELY FOR USE BY THE CHANGED MODULE. The green color coded rectangular area in the chart on the left represent the relatively simple task of re-implementing “Block D’s” logic when its HDL has been changed. The chart on the right demonstrates how other incremental design methodologies are required to take on the more challenging task of placing and routing a design within a fragmented region - presenting the additional challenges of where to locate the components AND what routing resources will be available for its use. Guide sees this: Instead of this: Result: Guide easily restores unchanged blocks in the design!
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Xilinx Modular Design Improves high-density design flows
Industry First Improves high-density design flows Faster time-to-market by enabling multiple designers to work on the design of a single device Changes task from high-density device design to high-performance module design Improves high-density design performance Enables more accurate / aggressive timing estimates during synthesis! Guaranteed module timing Enables a more robust incremental design flow Changes in HDL are retained within a module Modular design builds on the capabilities of Xilinx High-Level Floorplanning and enables a number of Engineers to independently work on the design of a single FPGA. Initially created to benefit customers creating Xilinx high-density FPGAs, Modular Design supports a complete FPGA design flow on individual modules within an FPGA. By focusing the design task on the creation and implementation of a function block, Modular Design helps focus individual designers on the task of creating high-performance modules, whose timing can be preserved when laying out the complete FPGA design using Xilinx modular design capabilities. Based on the same High-level Floorplanning technology, the Modular Design flow also helps synthesis partners like Synplicty achieve higher quality of results within each module’s design, resulting in even greater performance improvements through HDL synthesis. Finally, by its nature Modular Design creates the most robust incremental design flow available in the logic design industry. While Incremental synthesis isolates design changes to only the area that has changed, modular design goes once step further by enabling efficient what-if analysis in the implementation of a module, and allowing the updated module to be “checked in” to the design once a newer, higher-performance version of the module is completed.
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Xilinx Modular Design Enabling Autonomous Team Design
Design Flow Define modules In HDL block diagram Floorplan area for each design module Design, synthesize, place and route, and verify each module independently Run global routing to interconnect modules Modular Design allows different designers to work on the same FPGA independent of one another. The Design flow goes something like this: #1 - The system architect structures the top level design using VHDL or Verilog. This top level design must define the basic functionality of each block by defining its I/O. #2 - The Design is run through the first stage of Xilinx implementation tools, in order to enable the definition of area constraints for the various design modules. #3 - For each module, an area constraint is specified within the Xilinx Floorplanner. #4 - The Floorplan and Module specifications are then delegated to the various design engineers for the implementation of their individual modules. #5 - The individual design engineers then code, synthesize, and implement their design module to spec. Timing specifications for an individual module may be specified to enable timing driven place and route, or timing analysis. #6 - Once all design modules are completed, a Global Routing pass is performed to complete the project. Timing constraints may also be specified to address any critical timing for the global routing pass.
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Advanced Debug Capabilities
Industry Best Solves the debug bottleneck by Enabling in-system analysis of any internal FPGA signal while running at full system speed Easing analysis of any package pins (BGA) ChipScope ILA Powerful capture and control ILA cores Analysis at system speeds Comprehensive data capture Flexible trigger conditions Supports ILA modification without re-layout There are many factors that have driven the need for more comprehensive verification solutions for programmable logic design: Higher Density FPGAs Higher Performing FPGAs Higher integration of System level functions within FPGAs Higher Density Packaging of FPGA I/O pins Xilinx has created the industries best Integrated Logic Analysis tool in order to address the debug verification bottleneck. ChipScope ILA enables the in-system analysis of any signal that is available within the FPGA, while operating within the target system, and independent of the difficulties associated with probing today’s fine-pitch I/O packaging. ChipScope ILA is a silicon based analysis solution that is included as a core function within your design. Supported by the powerful Virtex architecture, ChipScope ILA enables the capture of a comprehensive set of data to be analyzed, based on powerful and flexible trigger conditions. If, after performing some logic analysis, you determine that there is a need to modify the data being captured, or the conditions for its capture, it is a simple matter of using the ILA PROBE capability within the FPGA Editor to make the changes, without requiring a complete design re-layout.
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The ChipScope ILA System
Control USER FUNCTION ILA Chipscope ILA MultiLINX PC with ChipScope MultiLINX Cable JTAG Connection Target Board Target FPGA with up to 15 ILA cores per control core ChipScope ILA is made up of 3 main components: ChipScope Software ILA Cores MultiLinx Download Cable Xilinx and Agilent worked together to make sure the ChipScope software has a look and feel that is common to Agilent Logic Analyzers. By creating a common look and feel, Xilinx has ensured that engineers who are familiar with the Agilent Logic Analyzers would feel comfortable when using the Xilinx ChipScope software. Additionally, Xilinx has created a feature within ChipScope which writes out analysis results in a format that is compatible with Agilent, enabling Xilinx customers to perform all of their analysis using the Agilent analyzers. The ILA Cores have been optimized to most efficiently take advantage of the Virtex and Spartan II architecture, enabling more comprehensive analysis when compared to other alternative solutions. The MultiLinx cable transfers data between the “host” PC and the target board via the JTAG port. Utilization of this existing test header, and I/O pins from the Xilinx devices results in greater efficiency of board and device I/O. The Multilinx cable is optionally supported by the USB port on many computers, enabling fast and efficient data transfers.
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ISE The Next Generation Design Environment
Design Hierarchy HDL Editor Language Templates Design Processes The control center of the ISE product is the Xilinx Project Navigator - the very same GUI that has made the Xilinx CPLD WebPack one of the most popular design tools of all time. The Project Navigator has 4 main windows that make it easy for you to manage your Xilinx design flow. The Design Hierarchy provides a simple browsing function so that you can easily see and understand all of the design source and target files that are associated with your project. Selections made within this window establish the “Context” for the available design proccesses that are displayed in the Design Processes window. The window is the editor area - in this case occupied with an HDL Editor and associated Language Templates. A Schematic editor may also be used within this area. The final window is the console, where Error Navigation to Web based solution records is simplified Error Navigation to Web Solutions
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Context Sensitive Flows
Powerful and easy to use Only relevant processes are displayed to the user Guides the user to the “next step” for that source HDL module selected Process available includes synthesis and place & route This slide illustrates a couple of examples of the context sensitive nature of the Process window. The top example shows that when an HDL Module is selected that a number of processes including synthesis, and place and route may be specified. The process window then takes control, understanding all of the file dependencies, and processing the HDL to your specified object file. The second example shows a simpler process operation - specifically that when an HDL testbench is selected, only an HDL simulator may be run. Again, the design process understands all of the file dependencies, compiling the necessary libraries and design and opening up the HDL simulator - in this case, ModelSim. HDL testbench select Only HDL simulation process is available
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Easy To Use Push Button Flows
Simple three step process to process design Design flow control manages dependencies 1 Add files The ISE project navigator - while different than the Foundation Series Project Control Manager - is a very easy to use, push-button design environment. In fact, it is so easy, that with three mouse clicks you can complete your design. In the first step you merely add your design source files. The second mouse click selects the top level design, and the third mouse click instructs the Project Navigator to generate the JTAG programming file and invoke the JTAG programmer. As simple as 1, 2, 3. 2 Select top level 3 Double click desired end point
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Easy to Use Error Navigation to Web
Automatically search solution records at support.xilinx.com Up-to-date expert answers for errors and warnings The Project Navigators Console window provides powerful navigation capabilities to the solutions records on support.xilinx.com. This comprehensive data base of answers is updates daily, enabling more and better navigation to solutions as design flow issues are uncovered after the release of our software. These solution records provide expert answers, and provide links to application notes that can make any designer even more productive. Gets the answers you need quickly!
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ISE Project Snapshots User created project checkpoints
Easily access any project snapshot User defined version/ revision scheme ISE also offers a capability to take a snapshot of your design, safley archiving for future use or reference. This snapshot not only includes implementation files like the old foundation series software, but it also captures all source and control files associated with your project. With project snapshots, you may find an RCS system is unecessary.
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Integrated Synthesis Environment
Integration of two advanced synthesis engines Maximize HDL design performance Synopsys FPGA Express OR Xilinx Synthesis Technology (XST) The Integrated Synthesis Environment provides two synthesis engines: FPGA Express and XST. Each of these tools is seamlessly integrated into the context sensitive flows that Project Navigator manages, making it simple to synthesize your HDL using two of the industry’s best HDL synthesis engines. Further optimizes your design’s performance!
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Timing Driven Synthesis
ISE Synthesis Engines Timing Driven Synthesis Schematic Viewer 4K Device Support Mixed Language RAM Inferencing Error Navigation Fanout Control Synthesis Flow X Express This graph illustrates the featrures of each ofthese synthesis engines. Note that while each tool supports many capabilities, only FPGA Express is capable of supporting mixed-language design, 4K device synthesis, and provides schematic viewing capabilities. XST on the other hand provides RAM inferenceing, an increasingly important feature with todays RAM rich FPGA architectures. X X X XST
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Xilinx Synthesis Technology An Added Bonus!
Focus on Quality of Results (QoR) Spartan-II, Virtex / E / EM / II, and 9500 only! Push-button results Xilinx speeds innovation with XST Vehicle to innovate integration with place and route Share exclusive technology with select partners Use as a secondary tool When better QoR is necessary Try on tough designs XST may be thought of as a secondary tool - with its focus squarly on delivering high quality results as a true synthesis engine. However, the benefits of XST do not stop there. You see Xilinx is using XST as a proving ground for many of the innovative optimization ideas that Xilinx engineers have for improving HDL design flows for Xilinx devices. These improvements are then shared with Xilinx 3rd party synthesis partners to ensure that anyone targeting Xilinx FPGAs as their solution can benefit from the best optimization the induistry has to offer.
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The ALLSTAR Program EDA ALLiance STARter
EDA Alliance partners tools that complement ISE Product support by ALLSTAR vendor Products targeted at lower density designs Functionally equivalent non-limited versions sold and supported by EDA partner The ISE product also benefits from a new partnering initiative that Xilinx began - the ALLSTAR program. The ALLSTAR program delivers real working 3rd party design tools within the ISE box, and integrated with the ISE solution. These real-world design tools will enable you to get real engineering work done while you are evaluating the benefits of the partners tools for YOUR as demonstrated in your ISE design flow. However, these tools are capacity or performance limited, so that they may be offered at no cost to you, as part of the Xilinx solution. If you find the ALLSTAR product to be beneficial, then you may purchase a performance or capacity upgrade, and continue to use the same GUIs that you had used with the ALLSTAR products.
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Technologies Delivered in ISE
Synopsys: FPGA Express FPGA Express version 3.4 Model Technology: ModelSim MXE starter & MXE delivered by Xilinx ModelSim PE and SE available from MTI Visual software solutions: StateCAD & Statebench HDL Bencher Xilinx Editions available in all packages Standard products available directly from Visual Software Solutions Partner technologies that are delivered in the ISE box include: Synopsys FPGA Express MTI: ModelSim XE Starter, XE, PE Eval and SE Eval\ VSS: State CAD, and HDL Bencher.
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Synopsys FPGA Express FPGA Express version 3.4 new features
Schematic Viewer “Find” feature Block Level Incremental Synthesis (BLIS) Xilinx exclusive feature User defined blocks within the design Individual netlists for each block only change if the source HDL has changed Virtex, VirtexE, Virtex2, Spartan2 Improved standard I/O support The latest release of Synopsys - FPGA Express 3.4 includes a variety of new features that improve the quality of results and runtimes that can be expected in your HDL design flow. Additionaly, the Schematic Viewer Find feature makes it easy to track down timing or functionality problems in the synthesized design, and linked to the source RTL. Synopsys has added a Xilinx exclusive feature - BLIS. BLIS makes it easy to converge on the required timing for your design by isolating design changes to within the HDL block that has changed. Combined with Xilinx high-level floorplanning, BLIS creates a robust flow for handling Engineering Change Orders (ECOs)
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Synopsys FPGA Express QoR Updated Install methodology for OEMs
ROM inferencing (implemented with dedicated RAM resources) Constant Arrays, certain CASE / if then else LUT instantiation Runtime improvements Updated Install methodology for OEMs Addressed issues raised with the 2.1i Foundation Install methodology Other improvements in the Synopsys product come from improving QoR by performing ROM inferencing, supporting LUT instanciations, and accelerating runtimes.
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