1. MonolithIC 3D Inc., Patents Pending MonolithIC 3D ICs February 2013 1 MonolithIC 3D Inc., Patents Pending

2. Content  Chapter 1 – MonolithIC 3D Chapter 1 – MonolithIC 3D  Chapter 2 – Laser Annealing  Chapter 3 - Monolithic 3D RCAT Chapter 3 - Monolithic 3D RCAT  Chapter 4 - Monolithic 3D HKMG Chapter 4 - Monolithic 3D HKMG  Chapter 5 - Monolithic 3D RC-JLT Chapter 5 - Monolithic 3D RC-JLT  Chapter 6 - Monolithic 3D eDRAM on Logic Chapter 6 - Monolithic 3D eDRAM on Logic  Chapter 7 - The Monolithic 3D Advantage Chapter 7 - The Monolithic 3D Advantage  Chapter 8 – Monolithic 3D DRAM Chapter 8 – Monolithic 3D DRAM MonolithIC 3D Inc. Patents Pending 2

3. 3 Chapter 1 Monolithic 3D

4. 3D ICs at a glance A 3D Integrated Circuit is a chip that has active electronic components stacked on one or more layers that are integrated both vertically and horizontally forming a single circuit. Manufacturing technologies: -Monolithic -TSV based stacking -Chip Stacking w/wire bonding MonolithIC 3D Inc, Patents Pending 4

5. MonolithIC 3D A technology breakthrough allows the fabrication of semiconductor devices with multiple thin tiers (<1um) of copper connected active devices utilizing conventional fab equipment. MonolithIC 3D Inc. offers solutions for logic, memory and electro- optic technologies, with significant benefits for cost, power and operating speed. MonolithIC 3D Inc., Patents Pending 5

6. Comparison of Through-Silicon Via (TSV) 3D Technology and Monolithic 3D Technology The semiconductor industry is actively pursuing 3D Integrated Circuits (3D-ICs) with Through-Silicon Via (TSV) technology (Figure 1). This can also be called a parallel 3D process. As shown in Figure 2, the International Technology Roadmap for Semiconductors (ITRS) projects TSV pitch remaining in the range of several microns, while on-chip interconnect pitch is in the range of 100nm. The TSV pitch will not reduce appreciably in the future due to bonder alignment limitations (0.5-1um) and stacked silicon layer thickness (6-10um). While the micron-ranged TSV pitches may provide enough vertical connections for stacking memory atop processors and memory-on-memory stacking, they may not be enough to significantly mitigate the well-known on- chip interconnect problems. Monolithic 3D-ICs offer through-silicon connections with <50nm diameter and therefore provide 10,000 times the areal density of TSV technology. MonolithIC 3D Inc., Patents Pending 6

7. MonolithIC 3D  Inc. Patents Pending 7 Typical TSV process  TSV diameter typically ~5um  Limited by alignment accuracy and silicon thickness Processed Top Wafer Processed Bottom Wafer Align and bond TSV Figure 1

8. Two Types of 3D Technology 8 3D-TSV Transistors made on separate wafers @ high temp., then thin + align + bond TSV pitch > 1um* Monolithic 3D Transistors made monolithically atop wiring (@ sub-400 o C for logic) TSV pitch ~ 50-100nm 10um- 50um 100 nm * [Reference: P. Franzon: Tutorial at IEEE 3D-IC Conference 2011]

9. Figure 2 ITRS Roadmap compared to monolithic 3D MonolithIC 3D Inc., Patents Pending 9

10. TSV (parallel) vs. Monolithic (sequential) MonolithIC 3D Inc., Patents Pending 10 Source: CEA Leti Semicon West 2012 presentationCEA Leti Semicon West 2012 presentation

11. The Monolithic 3D Challenge  Once copper or aluminum is added on for bottom layer interconnect, the process temperatures need to be limited to less than 400ºC !!!  Forming single crystal silicon requires ~1,200ºC  Forming transistors in single crystal silicon requires ~800ºC  The TSV solution overcame the temperature challenge by forming the second tier transistors on an independent wafer, then thinning and bonding it over the bottom wafer (‘parallel’) The limitations:  Wafer to wafer misalignment ~ 1µ  Overlaying wafer could not be thinned to less than 50µ

12. The Monolithic 3D Innovation  Utilize Ion-Cut (‘Smart-Cut’) to transfer a thin (<100nm) single crystal layer on top of the bottom (base) wafer  Form the cut at less than 400ºC *  Use co-implant  Use mechanically assisted cleaving  Form the bonding at less than 400ºC * * See details at: Low Temperature Cleaving, Low Temperature Wafer Direct BondingLow Temperature CleavingLow Temperature Wafer Direct Bonding  Split the transistor processing to two portions  High temperature process portion (ion implant and activation) to be done before the Ion-Cut  Low temperature (<400°C) process portion (etch and deposition) to be done after layer transfer See details in the following slides:

13. Monolithic 3D ICs Using SmartCut technology - the ion cutting process that Soitec uses to make SOI wafers for AMD and IBM (millions of wafers had utilized the process over the last 20 years) - to stack up consecutive layers of active silicon (bond first and then cut). Soitec’s Smart Cut Patented* Flow (follow this link for video).SmartCut Soitec’s Smart Cut Patented* Flow MonolithIC 3D Inc., Patents Pending 13 *Soitec’s fundamental patent US 5,374,564 expired Sep. 15, 2012

14. Monolithic 3D ICs Ion cuttingIon cutting: the key idea is that if you implant a thin layer of H+ ions into a single crystal of silicon, the ions will weaken the bonds between the neighboring silicon atoms, creating a fracture plane (Figure 3). Judicious force will then precisely break the wafer at the plane of the H+ implant, allowing you to in-effect peel off very thin layer. This technique is currently being used to produce the most advanced transistors (Fully Depleted SOI, UTBB transistors – Ultra Thin Body and BOX), forming monocrystalline silicon layers that are less than 10nm thick. MonolithIC 3D Inc., Patents Pending 14

15. Figure 3 Using ion-cutting to place a thin layer of monocrystalline silicon above a processed (transistors and metallization) base wafer MonolithIC 3D Inc., Patents Pending 15 p- Si Oxide p- Si Oxide H Top layer Bottom layer Oxide Hydrogen implant of top layer Flip top layer and bond to bottom layer Oxide p- Si Oxide H Cleave using <400 o C anneal or sideways mechanical force. CMP. Oxide Similar process (bulk-to-bulk) used for manufacturing all SOI wafers today p- Si

16. MonolithIC 3D Inc. Patents Pending 16 Chapter 2 Laser Annealing

17. 17 FD-SOI with Shielding Layers MonolithIC 3D Inc. Patents Pending Base Wafer Oxide-oxide bond Transferred Donor Layer Shielding Layers PMOS NMOS MonolithIC 3D Inc., Patents Pending

18. Excimer Laser 3D Annealing: Equipment available 18 MonolithIC 3D Inc., Patents Pending The 3D Thermal Processes Challenge SEMI & PV trends -Cost reduction -Yield increase -New Material -2D to 3D -Cost reduction -Yield increase -New Material -2D to 3D -Minimize Steps -Process uniformity -Material selectivity -Low thermal Budget -Minimize Steps -Process uniformity -Material selectivity -Low thermal Budget Process Flow + Pulsed Lasers + Wavelength selectivity + Single Die Anneal From EXCICO

19. 19 Activation of FD-SOI without Heating the Underneath Layers MonolithIC 3D Inc. Patents Pending Base Wafer Oxide-oxide bond Transferred Donor Layer Shielding Layers PMOS NMOS MonolithIC 3D Inc., Patents Pending Laser Pulse

20. MonolithIC 3D Inc. Patents Pending 20 Chapter 3 Monolithic 3D RCAT

21. MonolithIC 3D – The RCAT path  The Recessed Channel Array Transistor (RCAT) fits very nicely into the hot-cold process flow partition  RCAT is the transistor used in commercial DRAM as its 3D channel overcomes the short channel effect  Used in DRAM production @ 90nm, 60nm, 50nm nodes  Higher capacitance, but less leakage, same drive current The following slides present the flow to process an RCAT without exceeding the 400ºC temperature limit MonolithIC 3D Inc., Patents Pending 21

22. RCAT – a monolithic process flow MonolithIC 3D Inc., Patents Pending 22 Wafer, ~700µm ~100nm P- N+ P- Using a new wafer, construct dopant regions in top ~100nm and activate at ~1000ºC Oxide

23. MonolithIC 3D Inc. Patents Pending 23 ~100nm P- N+ P- Oxide Implant Hydrogen for Ion-Cut H+ Wafer, ~700µm

24. MonolithIC 3D Inc. Patents Pending 24 ~100nm P- N+ P- ~10nm H+ Oxide Hydrogen cleave plane for Ion-Cut formed in donor wafer Wafer, ~700µm

25. MonolithIC 3D Inc. Patents Pending 25 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer H+ Flip over and bond the donor wafer to the base (acceptor) wafer Base Wafer, ~700µm Donor Wafer, ~700µm

26. MonolithIC 3D Inc. Patents Pending 26 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer Perform Ion-Cut Cleave Base Wafer ~700µm

27. 27 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Complete Ion-Cut Base Wafer ~700µm

28. 28 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch Isolation regions as the first step to define RCAT transistors Base Wafer ~700µm

29. 29 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Fill isolation regions (STI-Shallow Trench Isolation) with Oxide, and CMP Base Wafer ~700µm

30. 30 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch RCAT Gate Regions Base Wafer ~700µm Gate region

31. 31 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Form Gate Oxide Base Wafer ~700µm

32. 32 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Form Gate Electrode Base Wafer ~700µm

33. 33 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Add Dielectric and CMP Base Wafer ~700µm

34. 34 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch Thru-Layer-Via and RCAT Transistor Contacts Base Wafer ~700µm

35. 35 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Fill in Copper Base Wafer ~700µm

36. 36 ~100nm N+ P- Oxide 1µ Top Portion of Base (acceptor) Wafer MonolithIC 3D Inc. Patents Pending Add more layers monolithically Base Wafer ~700µm Oxide ~100nm N+ P-

37. MonolithIC 3D Inc. Patents Pending 37 Chapter 4 Monolithic 3D HKMG

38. MonolithIC 3D Inc. Patents Pending 38 The monolithic 3D IC technology is applied to produce monolithically stacked high performance High-k Metal Gate (HKMG) devices, the world’s most advanced production transistors. 3D Monolithic State-of-the-Art transistors are formed with ion-cut applied to a gate-last process, combined with a low temperature face-up layer transfer, repeating layouts, and an innovative inter-layer via (ILV) alignment scheme. Monolithic 3D IC provides a path to reduce logic, SOC, and memory costs without investing in expensive scaling down. Technology

39. MonolithIC 3D Inc. Patents Pending 39 ~700µm Donor Wafer On the donor wafer, fabricate standard dummy gates with oxide and poly-Si; >900ºC OK PMOS NMOS Silicon Poly Oxide

40. MonolithIC 3D Inc. Patents Pending 40 ~700µm Donor Wafer Form transistor source/drain PMOS NMOS Silicon Poly Oxide

41. MonolithIC 3D Inc. Patents Pending 41 ~700µm Donor Wafer PMOSNMOS Silicon Form inter layer dielectric (ILD), do high temp anneals, CMP near to transistor tops CMP near to top of dummy gates ILD S/D Implant

42. MonolithIC 3D Inc. Patents Pending 42 ~700µm Donor Wafer PMOSNMOS Silicon Implant hydrogen to generate cleave plane

43. MonolithIC 3D Inc. Patents Pending 43 ~700µm Donor Wafer PMOSNMOS Silicon Implant hydrogen to generate cleave plane

44. MonolithIC 3D Inc. Patents Pending 44 ~700µm Donor Wafer PMOSNMOS Silicon Implant hydrogen to generate cleave plane H+

45. MonolithIC 3D Inc. Patents Pending 45 ~700µm Donor Wafer Silicon Bond donor wafer to carrier wafer H+ ~700µm Carrier Wafer

46. MonolithIC 3D Inc. Patents Pending 46 ~700µm Donor Wafer Cleave to remove bulk of donor wafer H+ ~700µm Carrier Wafer Transferred Donor Layer (nm scale) Silicon

47. MonolithIC 3D Inc. Patents Pending 47 CMP to STI ~700µm Carrier Wafer STI Transferred Donor Layer (<100nm)

48. MonolithIC 3D Inc. Patents Pending 48 Deposit oxide, ox-ox bond carrier structure to base wafer that has transistors & circuits ~700µm Carrier Wafer STI Oxide-oxide bond PMOS NMOS ~700µm Base Wafer Transferred Donor Layer (<100nm)

49. 49 Remove carrier wafer Oxide-oxide bond ~700µm Carrier Wafer MonolithIC 3D Inc. Patents Pending PMOS NMOS ~700µm Base Wafer Transferred Donor Layer (<100nm)

50. 50 Carrier wafer had been removed Oxide-oxide bond MonolithIC 3D Inc. Patents Pending PMOS NMOS ~700µm Base Wafer Transferred Donor Layer (<100nm)

51. 51 CMP to expose gate stacks. Replace dummy gate stacks with Hafnium Oxide & Metal (HKMG)at low temp Oxide-oxide bond MonolithIC 3D Inc. Patents Pending PMOS NMOS Note: Replacing the gate oxide and gate electrode results in a gate stack that is not damaged by the H+ implant ~700µm Base Wafer Transferred Donor Layer (<100nm)

52. 52 Form inter layer via (ILV) through oxide only (similar to standard via) Oxide-oxide bond MonolithIC 3D Inc. Patents Pending PMOS NMOS Note: The second mono-crystal layer is very thin (<100nm) and has a vertical oxide corridor; hence, the via through it (TLV) may be constructed and sized similarly to other vias in the normal metal stack. Transferred Donor Layer (<100nm) ~700µm Base Wafer

53. MonolithIC 3D Inc. Patents Pending 53 Form top layer interconnect and connect layers with inter layer via Oxide-oxide bond MonolithIC 3D Inc. Patents Pending PMOS NMOS ILV Transferred Donor Layer (<100nm) ~700µm Base Wafer

54. MonolithIC 3D Inc. Patents Pending 54 Maximum State-of-the-Art transistor performance on multi-strata 2x lower power 2x smaller silicon area 4x smaller footprint Performance of single crystal silicon transistors on all layers in the 3DIC Scalable: scales normally with equipment capability Forestalls next gen litho-tool risk High density of vertical interconnects enable innovative architectures, repair, and redundancy Benefits for RCAT and HKMG

55. MonolithIC 3D Inc. Patents Pending 55 Chapter 5 Monolithic 3D RC-JLT (Recessed-Channel Junction-Less Transistor )

56. MonolithIC 3D Inc. Patents Pending 56 Monolithic 3D IC technology is applied to producing monolithically stacked low leakage Recessed Channel Junction-Less Transistors (RC-JLTs). Junction-less (gated resistor) transistors are very simple to manufacture, and they scale easily to devices below 20nm: Bulk Device, not surface Fully Depleted channel Simple alternative to FinFET Superior contact resistance is achieved with the heavier doped top layer. The RCAT style transistor structure provides ultra-low leakage. Monolithic 3D IC provides a path to reduce logic, SOC, and memory costs without investing in expensive scaling down. Technology

57. RCJLT – a monolithic process flow MonolithIC 3D Inc., Patents Pending 57 Wafer, ~700µm ~100nm P- N++ N+ Using a new wafer, construct dopant regions in top ~100nm and activate at ~1000ºC Oxide

58. MonolithIC 3D Inc. Patents Pending 58 ~100nm P- Oxide Implant Hydrogen for Ion-Cut H+ Wafer, ~700µm N++ N+

59. MonolithIC 3D Inc. Patents Pending 59 ~100nm P- ~10nm H+ Oxide Hydrogen cleave plane for Ion-Cut formed in donor wafer Wafer, ~700µm N++ N+

60. MonolithIC 3D Inc. Patents Pending 60 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer H+ Flip over and bond the donor wafer to the base (acceptor) wafer Base Wafer, ~700µm Donor Wafer, ~700µm P-

61. MonolithIC 3D Inc. Patents Pending 61 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer Perform Ion-Cut Cleave Base Wafer ~700µm

62. 62 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Complete Ion-Cut Base Wafer ~700µm

63. 63 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch Isolation regions as the first step to define RCJLT transistors Base Wafer ~700µm

64. 64 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Fill isolation regions (STI-Shallow Trench Isolation) with Oxide, and CMP Base Wafer ~700µm

65. 65 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch RCJLT Gate Regions Base Wafer ~700µm Gate region

66. 66 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Form Gate Oxide Base Wafer ~700µm

67. 67 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Form Gate Electrode Base Wafer ~700µm

68. 68 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Add Dielectric and CMP Base Wafer ~700µm

69. 69 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch Thru-Layer-Via and RCJLT Transistor Contacts Base Wafer ~700µm

70. 70 ~100nm N++ N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Fill in Copper Base Wafer ~700µm

71. 71 ~100nm N++ N+ Oxide 1µ Top Portion of Base (acceptor) Wafer MonolithIC 3D Inc. Patents Pending Add more layers monolithically Base Wafer ~700µm Oxide ~100nm N++ N+

72. MonolithIC 3D Inc. Patents Pending 72 2x lower power 2x smaller silicon area 4x smaller footprint Layer to layer interconnect density at close to full lithographic resolution and alignment Performance of single crystal silicon transistors on all layers in the 3D IC Scalable: scales naturally with equipment capability Forestalls next gen litho-tool risk Also useful as Anti-Fuse FPGA programming transistors: programmable interconnect is 10x-50x smaller & lower power than SRAM FPGA Base logic circuits could be UT-BBOX, FinFET, or JLT CMOS logic devices Benefits for RCJLT

73. MonolithIC 3D Inc. Patents Pending 73 Create a layer of Recessed Channel Junction-Less Transistors (RC-JLTs), a junction-less version of the RCAT used in DRAMs, by activating dopants at ~1000°C before wafer bonding to the CMOS substrate and cleaving, thereby leaving a very thin doped stack layer from which transistors are completed, utilizing less than 400°C etch and deposition processes. RC-JLT flow: Summary

74. MonolithIC 3D Inc. Patents Pending 74 Chapter 6 Monolithic 3D eDRAM on Logic

75. MonolithIC 3D Inc. Patents Pending 75 Monolithic 3D eDRAM - Technology Monolithic 3D IC technology is applied to producing monolithically stacked low leakage Recessed Channel Array Transistors (RCATs) with stacked capacitors (eDRAM) on top of logic. Cost savings through a footprint reduction of 75% and an active silicon area reduction of 50% can be obtained by monolithically stacking the eDRAM on top of logic. The eDRAM and logic device layers can be independently optimized; hence, no more wasting 10 metal layers on DRAM die area. In addition, monolithic stacking enables the use of DRAM for the memory, which is 3 times more area efficient than SRAM. RCATs can be used for memory cells and decoder logic. As well, an independent refresh port allows reduced voltage and power. Short wires and close proximity of the eDRAM to logic provides maximum performance.

76. SoC Device Architecture (Part 1)  Pull out the memory to the second layer  About 50% of a typical SoC is embedded memory, and about 50% of the logic area is due to gate sizing buffers and repeaters.  Going monolithic 3D eliminates majority of buffers and repeaters  Therefore, 2 stack monolithic:  => A Base layer with just the logic (hence, 25% of original SoC area)  => 2 nd layer has the eDRAM with stack capacitor  RESULT: 3D silicon footprint is about 25% of original 2D! 76

77. SoC Device Architecture (Part 2)  25% of the area of eDRAM (1T) needs to replace 50% of the equivalent SRAM  1T vs. ½ of 6T ~ 1:3, could be used for:  Use older node for the eDRAM, with optional additional port for independent refresh  Additional advantage for dedicated layer of eDRAM  Optimized process  Only 3 metal layers, no die area wasted on logic 10 metal layers  Repetitive memory structure – easy for litho and fab 77

78. 2D SoC to Monolithic 3D (eDRAM on top of Logic) 2D SoC 3D SoC 7mm 14mm Logic + Memory Logic Memory Footprint = 196mm 2 Footprint = 49mm 2 78

79. eRAM portion in SoC MonolithIC 3D Inc. Patents Pending 79

80. Monolithic 3D SoC Side View Base wafer with Logic circuits RCAT transistors (eDRAM + Decoders ) Stack Capacitors (for eDRAM) Logic circuits 80 Base wafer with Logic circuits

81. eDRAM  Use RCAT for bit cell and decoders Bit Line WL Vdd Bit Line WL WL-Refresh  eDRAM with independent port for refresh 81

82. eDRAM vs SRAM on top  Smaller area and shorter lines will result in competitive performance  Independent port for refresh will allow reduced voltage and therefore comparable power 82

83. 3D eDRAM – a monolithic process flow MonolithIC 3D Inc., Patents Pending 83 Wafer, ~700µm ~100nm P- N+ P- Using a new wafer, construct dopant regions in top ~100nm and activate at ~1000ºC Oxide

84. MonolithIC 3D Inc. Patents Pending 84 ~100nm P- N+ P- Oxide Implant Hydrogen for Ion-Cut H+ Wafer, ~700µm

85. MonolithIC 3D Inc. Patents Pending 85 ~100nm P- N+ P- ~10nm H+ Oxide Hydrogen cleave plane for Ion-Cut formed in donor wafer Wafer, ~700µm

86. MonolithIC 3D Inc. Patents Pending 86 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer H+ Flip over and bond the donor wafer to the base (acceptor) wafer Base Wafer, ~700µm Donor Wafer, ~700µm P-

87. MonolithIC 3D Inc. Patents Pending 87 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer Perform Ion-Cut Cleave Base Wafer ~700µm

88. 88 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Complete Ion-Cut Base Wafer ~700µm

89. 89 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch Isolation regions as the first step to define RCAT transistors Base Wafer ~700µm

90. 90 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Fill isolation regions (STI-Shallow Trench Isolation) with Oxide, and CMP Base Wafer ~700µm

91. 91 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch RCAT Gate Regions Base Wafer ~700µm Gate region

92. 92 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Form Gate Oxide Base Wafer ~700µm

93. 93 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Form Gate Electrode Base Wafer ~700µm

94. 94 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Add Dielectric and CMP Base Wafer ~700µm

95. 95 ~100nm N+ P- Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Etch Thru-Layer-Via and RCAT Transistor Contacts Base Wafer ~700µm TLV

96. MonolithIC 3D Inc. Patents Pending 96 Complete wires and TLVs, and form stacked capacitors TLV Stacked Capacitor

97. MonolithIC 3D Inc. Patents Pending 97 Create a layer of Recessed ChAnnel Transistors (RCATs), commonly used in DRAMs, by activating dopants at ~1000ºC before wafer bonding to the CMOS substrate and cleaving, thereby leaving a very thin doped stack layer from which transistors are completed, utilizing less than 400ºC etch and deposition processes. Add stacked caps. eDRAM on logic flow

98. MonolithIC 3D Inc. Patents Pending 98 2x lower power 2x smaller silicon area 4x smaller footprint Replacing SRAM with eDRAM reduces memory costs by up to 2/3 Can use older and cheaper process node for eDRAM and use optimum number of metal layers, incurring no waste Layer to layer interconnect density at close to full lithographic resolution and alignment Scalable: scales naturally with equipment capability Forestalls next gen litho-tool risk Base logic circuits could be UT-BBOX, FinFET, or JLT CMOS logic devices. Logic transistors are untouched by DRAM (such as trench) processing Benefits for 3D eDRAM

99. MonolithIC 3D Inc. Patents Pending 99 Chapter 7 The Monolithic 3D Advantage

100. MonolithIC 3D Inc. Patents Pending 100 Monolithic 3D is far more than just an alternative to 0.7x scaling!!!

101. MonolithIC 3D Inc. Patents Pending 101 1. Introduction Over the last 50 years we have seen tremendous technological and economic progress in semiconductors and microelectronics following what is known as Moore's Law. Accordingly about every two years the amount of transistors we can integrate on an IC doubles. This exponential increase in integration is achieved by scaling down the dimensions of the microcircuit by a factor of 0.7 at every technology node. For most of that half-century the scaling was relatively easy and was associated with about a 30% reduction of the transistor cost, a greatly improved performance, and markedly reduced power consumption. For most of us who have lived and worked this scaling - 'those were the days!'

102. MonolithIC 3D Inc. Patents Pending 102 1. Introduction However, recently the trend has changed dramatically, and it is now harder and harder (technically and economically) to achieve dimensional scaling; and as a result, there are diminishing improvements in transistor costs, power or performance. We discuss many of the details on our blogs: IEDM: Moore’s Law seen hitting big bump at 14 nm Is the Cost Reduction Associated with Scaling Over? Entanglement Squared IEDM 2012 - The Pivotal Point for Monolithic 3D IC

103. MonolithIC 3D Inc. Patents Pending 103 1. Introduction A new form of scaling is shaping up as an alternative to maintain the exponential increase in integration. This new form is scaling up using monolithic 3D technology. The NAND Flash vendors are the early adopters of this new alternative scaling with multiple variations of products being developed that are scheduled to reach volume production in 2015. In the following we will present "The Monolithic 3D" advantage. It is possible that this new technology could return us to the trend we had enjoyed before with reductions of cost, decreases in power consumption, and improvements in performance, and bring some new and compelling benefits.

104. MonolithIC 3D Inc. Patents Pending 104 1. Introduction Specifically, these are:  Continuing reductions in die size and power  Significant advantages for reusing the same fab line and design tools  Heterogeneous Integration  Processing multiple layers simultaneously, offering multiples of cost improvement  Logic redundancy, allowing 100x integration at good yields  Modular Platforms

105. MonolithIC 3D Inc. Patents Pending 105 2. Reduction in die size and power A.Reduction in die size Dimensional scaling has always been associated with increased wire resistivity and capacitance. Every node of dimensional scaling is associated with larger output drivers and more buffers and repeaters. The following charts illustrate the rapid increase of the number of transistors associated with the increased interconnect challenge. Source: ISQED07 Alam

106. MonolithIC 3D Inc. Patents Pending 106 2. Reduction in die size and power

107. MonolithIC 3D Inc. Patents Pending 107 2. Reduction in die size and power Monolithic 3D enables the folding of a circuit, with the each stratum only about 1µ above or below its neighbor, combined with a very rich vertical connectivity between the strata. The following IBM/MIT slide illustrates the effectiveness of such a folding.

108. MonolithIC 3D Inc. Patents Pending 108 2. Reduction in die size and power Further, the reduced silicon area generates an additional reduction of buffers and the average transistor size. MonolithIC 3D Inc. released an open-source high level simulator IntSim v2.0 to simulate a given design’s expected size and power based on process parameters and the number of strata. More than 400 copies have been downloaded so far. Using the simulator we can see in the following table that a 2D design of 50 mm2 area with an average gate size of 6 W/L, will only need an average gate size of 3 W/L and accordingly only 24 mm2 of total circuit area if folded into two strata (the footprint will be therefore just 12 mm2).

109. MonolithIC 3D Inc. Patents Pending 109 2. Reduction in die size and power These results are in-line with many other monolithic 3D research results. => Monolithic 3D 'folding' reduces the device silicon size by ~50% and leads to a similar reduction in transistor cost.

110. MonolithIC 3D Inc. Patents Pending 110 2. Reduction in die size and power B. Reduction in power The following chart illustrates that interconnect is now dominating the device power. =>As every 'folding' effectively reduces the average wire length by about 50% it results in reducing the average power by 50%. (Note: This assumes a proportional increase in complexity, which the industry has consistently done)

111. MonolithIC 3D Inc. Patents Pending 111 3. Significant advantages for using the same fab and design tools A.Depreciation With dimensional scaling every technology/process node requires a significant capital investment for new processing equipment, significant R&D spending for new transistor process and device development, and the building of an ever more complex and costly library and EDA flow. The following charts illustrate this escalating cost trend:

112. MonolithIC 3D Inc. Patents Pending 112 3. Significant advantages for using the same fab and design tools With monolithic 3D these costs are not required as dimensions are maintained for multiple generations and only the number of strata or layers is increased. If the industry could use the same equipment and the same transistors and libraries for 4 years instead of 2, then all these costs could be depreciated over a longer time, with resulting significant cost benefits.

113. MonolithIC 3D Inc. Patents Pending 113 3. Significant advantages for using the same fab and design tools The following chart portion demonstrates the reduction of transistor cost per node as yield improves and equipment cost depreciates

114. MonolithIC 3D Inc. Patents Pending 114 3. Significant advantages for using the same fab and design tools B. Learning Curve – Yield Using the same transistor tools and EDA has an additional important benefit. Learning curve equals yield improvement. With dimensional scaling we face the predicament that by the time we know how to manufacture a process node well, that learning quickly becomes obsolete as we are quickly moving on to the next node. With monolithic 3D, the learning of the previous node stacking is directly utilized on the integration development of more strata, rather than on new materials, design tool issues, etc. The following chart illustrates the dimensional scaling trend:

115. MonolithIC 3D Inc. Patents Pending 115 3. Significant advantages for using the same fab and design tools Each node of scaling is taking longer and costing more to get to mature yield (‘ramped-up’)

116. MonolithIC 3D Inc. Patents Pending 116 3. Significant advantages for using the same fab and design tools The design and litho based yield loss is growing quickly as the technology node gets dimensionally smaller.

117. MonolithIC 3D Inc. Patents Pending 117 4. Heterogeneous Integration 3D IC enables far more than an alternative for increased integration. It provides another dimension of design flexibility. A well-known aspect of this flexibility is the ability to split the design into layers which could be processed and operated independently, and still be tightly interconnected - especially for monolithic 3D. The following figure illustrates the ability to use different substrate crystal and different type of devices in such a heterogeneous integration.

118. MonolithIC 3D Inc. Patents Pending 118 4. Heterogeneous Integration A.Logic, Memory, IO Let’s start with quoting Mark Bohr, in charge of Intel’s process development: "Bohr: One important perspective is that chip technology is becoming more heterogeneous. If you go back 10 or 20 years ago, it was homogenous. There was a CMOS transistor, it was the same materials for NMOS and PMOS, maybe different dopant atoms, and that basic CMOS transistor fit the needs of both memory and logic. Going forward we’ll see chips and 3D packages that combine more heterogeneous elements, different materials, and maybe transistors with very different structures whether they’re for logic or memory or analog. Combining these very different devices onto one chip or into a 3D stack—that’s what we’ll see. It will be heterogeneous integration"Bohr:

119. MonolithIC 3D Inc. Patents Pending 119 4. Heterogeneous Integration The most important market for semiconductor products is smart mobility. For this market the SoC device needs to integrate many functions, such as logic, memory, and analog. In most cases the pure high-performance logic would be about 25% of the die area, 50% of the area would be memory, and the rest would be analog functions such as I/O, RF, and sensors.

120. MonolithIC 3D Inc. Patents Pending 120 4. Heterogeneous Integration In 2D all the functions need to be processed together and bear the same manufacturing costs. In a monolithic 3D-IC stack using heterogeneous integration each stratum is processed in an optimized flow, allowing for a significant cost reduction and no loss in optimized performance for each function type. The following illustration suggests the use of only two strata to build a device that in 2D would have a size of 196 mm 2. By having one stratum for logic and one for memory, and by using DRAM instead of SRAM, the device could be reduced to 98 mm 2 with footprint of 49 mm 2. The device cost would be further reduced by the memory using only 3 or 4 metal layers. eDRAM on logiceDRAM on logic

121. MonolithIC 3D Inc. Patents Pending 121 4. Heterogeneous Integration

122. MonolithIC 3D Inc. Patents Pending 122 4. Heterogeneous Integration B. Strata of Logic The logic itself could be constructed better using heterogeneous integration. In many cases only portion of the logic need to be high performance while other portion could be better – and cheaper – done using older process node. Other scenarios could include designing different strata with different supply voltages for power savings, different number of metal interconnect layers, or other variations in the design space. C. Strata of different substrate crystals and fabrication processes. 3D enabled heterogeneous integration could be used as illustrated in the beginning of the chapter. Some layers could utilize silicon while other might use compound semiconductors. Some layers could be image sensors or other type of electro-optic structures and so forth.

123. MonolithIC 3D Inc. Patents Pending 123 5. Multiple Layers Processed Together An extremely powerful unique advantage of monolithic 3D is the option to process multiple layers in parallel following one lithography step. This option is most natural for regular circuits such as memory, but it is also available for logic circuits. The driver for this option is the escalating costs of lithography in state of the art IC. The following illustration presents the impact of dimensional scaling on lithography costs.

124. MonolithIC 3D Inc. Patents Pending 124 5. Multiple Layers Processed Together Currently the critical lithography steps dominate the end device production costs. Accordingly, if the critical lithography step could be used once for multiple layers rather than multiple times for each single layer, then the end device cost would roughly be reduced in proportion to the number of layers processed simultaneously. The first merchants to recognize this option and who are moving to monolithic 3D are the NAND Flash vendors, as illustrated in the next figure.

125. MonolithIC 3D Inc. Patents Pending 125 5. Multiple Layers Processed Together Using the proper architecture, multiple transistor layers could be processed together with a huge reduction in cost per layer. This could be applied to many different types of regular devices. The following illustrates the concept applied to a floating-body DRAM:

126. MonolithIC 3D Inc. Patents Pending 126 5. Multiple Layers Processed Together

127. MonolithIC 3D Inc. Patents Pending 127 6. Logic redundancy allowing 100x integration with good yield The strongest value of an IC is the integration of many functions in one device. This is and will be the most important driver of Moore's Law because by integrating functions into one IC we achieve orders of magnitude benefits in power, speed, and costs. At any given technology node the limiting factor to integration is yield. As yield relates strongly to device area, most vendors are trying to limit the die size to about 50mm²-100 mm². Some product applications require an extremely large die of over 600mm², but those are rare (and high value-add) cases because the yield goes down exponentially as die size grows. While memory redundancy is prevalent in the IC industry, logic redundancy is only used in a few FPGAs – no solution has been found after the failure of Trilogy, where “Triple Modular Redundancy" was employed systematically. Every logic gate and every flip-flop were triplicated with binary two-out-of-three voting at each flip-flop. Quoting Gene Amdahl : “Wafer scale integration will only work with 99.99% yield, which won’t happen for 100 years.” (Source: Wikipedia)

128. MonolithIC 3D Inc. Patents Pending 128 6. Logic redundancy allowing 100x integration with good yield An additional advantage of monolithic 3D is the ability to construct redundancy for circuits including logic, with minimal impact on the design process and while maintaining circuit performance. The concept is illustrated in the following figure:

129. MonolithIC 3D Inc. Patents Pending 129 6. Logic redundancy allowing 100x integration with good yield There are three primary ideas here: Swap at logic cone granularity. Redundant logic cone/block directly above, so no performance penalty. Negligible design effort, since the redundant layer is an exact copy. The new concept leverages two important technology breakthroughs. The first is the Scan Chain technology that enables a circuit test where faults are identified at the logic cone level. The second is the monolithic 3D IC which enables a fine-grained redundancy: replacement of a defective logic cone by the same logic cone that is only ~1 micron above. Accordingly, by just building the same circuit twice, one on top of the other, with minimal overhead, every fault could be repaired by the replacement logic cone above. Such repair should have a negligible power penalty and a minimal cost penalty whenever the base circuit yield is about 50%. There should be almost no extra design cost and many additional benefits can be obtained.

130. MonolithIC 3D Inc. Patents Pending 130 6. Logic redundancy allowing 100x integration with good yield This redundancy technique could be also used to repair faults throughout the device life-time, including in the field, which is a powerful advantage. So the immediate question should be: how far can we go with such an approach? A simple back-of-the-envelope calculation should start with the number of flip- flops in a modern design. In today's designs we expect more than one million F/F (and their logic cones). Consequently, if we expect one defect, then a device with redundancy layer would work unless the same cone is faulty on both layers, which probability-wise would be one in a million! Clearly we have removed yield as a constraint to super-scale integration. We could even integrate 1,000 such devices!!!

131. MonolithIC 3D Inc. Patents Pending 131 6. Logic redundancy allowing 100x integration with good yield The ultra-integration value could be as much as:  ~10X Advantage of 3D WSI vs. 2D @ Board Level  ~10X Advantage of 3D WSI vs. 2D @ Rack Level  ~10X Advantage of 3D WSI vs. 2D @ Server Farm Level Overall, a ~1000x advantage is possible, all due to shorter wires. Instead of placing chips on different packages, boards and racks, we integrate on the same stacked chip.

132. MonolithIC 3D Inc. Patents Pending 132 7. Modular Platform The 3D monolithic device would be a good fit to platform-based designs wherein some part of the device is used by all customers and others are tailored to a specific market/customer segment as illustrated by the following figure. Such a system architecture could be inexpensively used in many market segments and with multiple variations. An interesting one could be in the FPGA sector where the same platform could come with many flavors of memories and I/O.

133. MonolithIC 3D Inc. Patents Pending 133 8. Other ideas There are other powerful advantages to monolithic 3D including those that we will discover in the future. In this chapter we present some specific applications where monolithic 3D provides significant advantages. A. Image sensor with Pixel electronics The image sensor industry has moved to back-side illumination to increase the image sensor area utilization. By adding the option for multiple layers many additional benefits could be gained as illustrated below:

134. MonolithIC 3D Inc. Patents Pending 134 8. Other ideas B. Micro-display The display market is always looking to reduce power and size while increasing the resolution and brightness. Monolithic 3D could provide ultra-high resolution with extreme power efficiency and minimal size, by combining drive electronics with layers of different color light emitting diodes as is illustrated below.

135. MonolithIC 3D Inc. Patents Pending 135 8. Other ideas C. SOI (FD-SOI) The upper layer of monolithic 3D devices are naturally Silicon-On-Insulator (SOI). The advantage of SOI is well known and the recent progress of Fully Depleted SOI (FD-SOI) and SOI-FinFet has taken that advantage much further as illustrated below. Source: ST-Ericsson

136. MonolithIC 3D Inc. Patents Pending 136 9. Summary Monolithic 3D is a disruptive semiconductor technology. It builds on the existing infrastructure and know-how, and could bring to the high tech industry many more years of continuous progress. While it provides the advantages that dimensional scaling once provided, monolithic 3D offers many more options and benefits. And the best of all is that it could be done in conjunction with dimensional scaling. Now that monolithic 3D is practical, it is time to augment dimensional scaling with monolithic 3D-IC scaling.

137. MonolithIC 3D Inc. Patents Pending 137 Chapter 8 Monolithic 3D DRAM

138. Key technology direction for NAND flash: Monolithic 3D with shared litho steps for memory layers To be viable for DRAM, we require  Single-crystal silicon at low thermal budget  Charge leakage low  Novel monolithic 3D DRAM architecture with shared litho steps MonolithIC 3D Inc. Patents Pending 138 Toshiba BiCS Poly Si Samsung VG- NAND Poly Si Macronix junction-free NAND Poly Si

139. Single crystal Si at low thermal budget  Obtained using the ion-cut process. It’s use for SOI shown above.  Ion-cut used for high-volume manufacturing SOI wafers for 10+ years. MonolithIC 3D Inc. Patents Pending 139 Activated p Si Oxide H Top layer Bottom layer Oxide Hydrogen implant of top layer Flip top layer and bond to bottom layer Oxide H Cleave using 400 o C anneal or sideways mechanical force. CMP. Oxide Activated p Si Silicon Top layer

140. Double-gated floating body memory cell well-studied in Silicon (for 2D-DRAM)  0.5V, 55nm channel length  900ms retention  Bipolar mode MonolithIC 3D Inc. Patents Pending 140 Hynix + Innovative Silicon VLSI 2010 Intel IEDM 2006  2V, 85nm channel length  10ms retention  MOSFET mode

141. MonolithIC 3D Inc. Patents Pending 141 Monolithic 3D IC technology can be applied to producing a monolithically stacked single crystal silicon double-gated floating body DRAM memory. Lithography steps are shared among multiple memory layers. Peripheral circuits below the monolithic memory stack provide control functions. Reduce DRAM bit cost without investing in expensive scaling down. Technology

142. MonolithIC 3D Inc. Patents Pending 142 Monolithic 3D DRAM

143. Our novel DRAM architecture MonolithIC 3D Inc. Patents Pending 143 n+ Gate Electrode Gate Dielectric p SiO 2 Innovatively combines these well-studied technologies  Monolithic 3D with litho steps shared among multiple memory layers  Stacked Single crystal Si with ion-cut  Double gate floating body RAM cell (below) with charge stored in body

144. Process Flow: Step 1 Fabricate peripheral circuits followed by silicon oxide layer Silicon Oxide Peripheral circuits with W wiring

145. Process Flow: Step 2 Transfer p Si layer atop peripheral circuit layer Silicon Oxide p Silicon H implant Silicon Oxide Peripheral circuits Silicon Oxide Peripheral circuits Top layer Bottom layer Silicon Oxide p Silicon H implant Flip top layer and bond to bottom layer

146. Process Flow: Step 3 Cleave along H plane, then CMP Silicon Oxide Peripheral circuits Silicon Oxide p Silicon Silicon Oxide Peripheral circuits

147. Process Flow: Step 4 Using a litho step, form n+ regions using implant Silicon Oxide Peripheral circuits Silicon Oxide p n+n+ n+n+ n+n+ p

148. Process Flow: Step 5 Deposit oxide layer Silicon Oxide Peripheral circuits Silicon Oxide n+ p

149. Process Flow: Step 6 Using methods similar to Steps 2-5, form multiple Si/SiO 2 layers, RTA Silicon Oxide Peripheral circuits Silicon Oxide 06 Silicon Oxide Silicon Oxide 06 Silicon Oxide Silicon Oxide 06 Silicon Oxide pn+

150. Process Flow: Step 7 Use lithography and etch to define Silicon regions Silicon Oxide Peripheral circuits p Silicon Silicon Oxide 06 Silicon oxide Symbols n+ Silicon This n+ Si region will act as wiring for the array… details later

151. Process Flow: Step 8 Deposit gate dielectric, gate electrode materials, CMP, litho and etch Silicon Oxide Peripheral circuits n+ Silicon Silicon Oxide 06 Silicon oxide Symbols Gate electrode Gate dielectric

152. Process Flow: Step 9 Deposit oxide, CMP. Oxide shown transparent for clarity. Silicon Oxide Peripheral circuits Silicon Oxide 06 Silicon oxide Word Line (WL) WL current path SL current path Source-Line (SL) n+ Silicon Silicon oxide Symbols Gate electrode Gate dielectric Silicon oxide

153. Process Flow: Step 10 Make Bit Line (BL) contacts that are shared among various layers. Silicon Oxide Peripheral circuits Silicon Oxide 06 Silicon oxide WL SL WL current path SL current path BL contact n+ Silicon Silicon oxide Symbols Gate electrode Gate dielectric Silicon oxide BL contact

154. Process Flow: Step 11 Construct BLs, then contacts to BLs, WLs and SLs at edges of memory array using methods in [Tanaka, et al., VLSI 2007] Silicon Oxide Peripheral circuits n+ Silicon Silicon Oxide 06 Silicon oxide Symbols Gate electrode Gate dielectric Silicon oxide WL SL SL current BL contact BL WL current BL current BL

155. Some cross-sectional views for clarity. Each floating-body cell has unique combination of BL, WL, SL

156. A different implementation: With independent double gates BL BL contact Silicon Oxide 06 p Silicon Silicon oxide n+ Silicon Periphery WL wiring Gate dielectric Gate electrode BL WL SL

157. MonolithIC 3D Inc. Patents Pending 157 3.3X the density of conventional stacked capacitor DRAM Same number of litho steps as conventional stacked cap DRAM Single crystal silicon on all layers Scalable: Multiple generations of cost-per-bit improvement for same equipment cost and process node: use the same fab for 3 generations Forestalls next gen litho-tool risk Avoids the red bricks and costs of capacitor scaling & new cell transistor development Benefits

158. MonolithIC 3D Inc. Patents Pending 158 © Copyright MonolithIC 3D Inc., the Next- Generation 3D-IC Company, 2013 - All Rights Reserved, Patents Pending