1. Kick-Off Meeting Catania – February 26, 2010 THERMINATOR Modeling, Control and Management of Thermal Effects in Electronic Circuits of the Future

2. Enrico Macii -- enrico.macii@polito.it 2 Agenda, February 26 th 2010 09:00 Welcome and Project highlightsS. Rinaudo ­ Round-table and presentation of each partner 10:00 Technical Work Plan walk-throughE. Macii ­ Deploy the operative workplan (part 1) ­ Milestones, Deadlines, Gantt Discussion and Agreement of Project Handbook ­ Scheduling the main governance’s Meetings 11:30 Project management overview and IPRG. Gangemi ­Project Management structure and Handbook ­IPCA and IPs 11:45 Training WorkplanN. Gergely 12:00 Deploy the operative workplan (part 2)E. Macii ­ R&D, Roadmap, dissemination 12:30 Lunch Break 13:30 Deploy the operative workplan (part 3)E. Macii ­ Technical dependencies and links among partners 16:00 THERMINATOR Management issuesR. Zafalon ­ Press Release: draft preparation (To issue by April 2010) ­ Pending issues to be agreed ­ Money transferring policy from coordinator’s account to partners 17:30 Final Wrap-up & Action Items

3. Project Overview E. Macii (POLITO)

4. Enrico Macii -- enrico.macii@polito.it 4 Objectives and Consortium The Objectives 1.Development of new modeling and simulation capabilities. 2.Development of new thermal- aware design techniques, methodologies and prototype tools 3.Validation of thermal model accuracy against silicon measurements 4.Assessment of results of application of thermal-aware design solutions on test-chips. 5.Assessment of results of application of thermal-aware EDA prototype tools on industry- strength design cases. STM, NXP, IFX BME, CSEM, FHG, IMEC, CEA-LETI, OFFIS, POLITO, UNIBO CV,GDA,MUN,SNPS IC Vendors Research Institutes EDA Vendors The Consortium 15 partners

5. Enrico Macii -- enrico.macii@polito.it 5 Therminator Platform System-level thermal modeling and simulation Design Simulation, Modeling Package thermal modeling Thermal-Aware design exploration Package selection Thermal Interconnect modeling Logi-Thermal Simulation Thermal-Aware Synthesis Circuit-level thermal modeling and simulation Thermal Modeling and Thermal- Aware Simulation Device Characterization and Thermal Compact Modeling analog/RFdigital discrete systems blocks or components circuits devices Thermal-Aware Design Using Advanced Technologies Architecture- level Thermal modeling Thermal Management of digital blocks Thermal compensation for interconnects Exploration Temperature- Insensitive Library Block-level thermal modelling and simulation

6. Enrico Macii -- enrico.macii@polito.it 6 Workplan Start date: 01/01/10 Duration: 36 months Effort: 944 p/m Cost: 11 M€ EC funding: 6.4 M€ WP1: Technology Characterization, Tool Requirements and Test Case Identification WP2: Process, Device and Compact Modeling WP3: Modeling, Simulation and Design of Digital Blocks WP4: Modeling and Simulation of Analog/RF Blocks WP5: Modeling and Simulation of Discrete Components WP7: Validation, Demonstration and Evaluation WP8: Dissemination, Training, Exploitation and Roadmapping WP6: Package/System Modeling and Design Exploration under Ambient Influence WP9: Project Management RTD DEM MGT

7. Enrico Macii -- enrico.macii@polito.it 7 Workplan WPWP Title Type of Activity LeaderEFFORT Start Month End Month Deliv. 1 Technology Characterization, Tool Requirements and Test Case Identification RTDIFX72M1M24 From: D1.1.1 To: D1.3.2 2 Process, Device and Compact Modeling RTDIFX104M1M24 From: D2.1.1 To: D2.3.4 3 Modeling, Simulation and Design of Digital Blocks RTDPOLITO201M1M30 From: D3.1.1 To: D3.4.3 4 Modeling and Simulation of Analog/RF Blocks RTDNXP72M1M30 From: D4.1.1 To: D4.2.3 5 Modeling and Simulation of Discrete Components RTDST62M1M30 From: D 5.1.1 To: D5.2.1 6 Package/System Modeling and Design Exploration under Ambient Influence RTDNXP221M1M30 From: D6.1.1 To: D6.3.3 7 Validation, Demonstration and Evaluation DEMNXP116M19M36 From: D7.1.1 To: D7.3.2 8 Dissemination, Training, Exploitation and Roadmapping RTDST62M1M36 From: D8.1.1 To: D8.4.11 9Project ManagementMGTST34M1M36 From: D9.1.1 To: D9.4.4 TOTAL944

8. Enrico Macii -- enrico.macii@polito.it 8 Gantt Chart

9. R&D Activities (WP1, WP2, WP3, WP4, WP5, WP6)

10. Enrico Macii -- enrico.macii@polito.it 10 WP1 (Leader: IFX) WP1: Technology Characterization, Tool Requirements and Test Case Identification ­T1.1: Technology Characterization Investigation and characterization of a wide collection of different nanoelectronic technologies and device architectures regarding temperature sensitivity and thermal effects ­T1.2: Tool Requirements Specification of the requirements for the EDA methodologies, tools and flows that will be developed within the project ­T1.3: Test Case Identification Identification by the semiconductor vendors of the test structures and of the test cases that will be used to assess the quality of the models, design solutions and EDA methodologies and prototype tools

11. Enrico Macii -- enrico.macii@polito.it 11 WP1 (Leader: IFX) TaskDurationPartners Involved T1.1M1-M24IFX, ST, NXP T1.2M1-M3MUN, CV, GDA, SNPS, ST, IFX, NXP T1.3M1-M12ST, IFX, NXP

12. Enrico Macii -- enrico.macii@polito.it 12 WP1 (Leader: IFX)

13. Enrico Macii -- enrico.macii@polito.it 13 WP2 (Leader: IFX) WP2: Process, Device and Compact Modeling ­T2.1: Compact thermal modeling of new device structures and technologies Development of methods for numerical simulation of devices that utilize new semiconductor structures and technologies, down to the 32/28nm process node. ­T2.2: Compact thermal modeling of CMOS devices for integrated circuits Development of methods for numerical simulation of devices for integrated circuits implemented with traditional, state-of-the-art CMOS technologies. ­T2.3: Physics-based compact thermal modeling for discrete devices Development of methods for numerical simulation of devices for discrete semiconductor devices, specifically suitable for power converters and RF applications.

14. Enrico Macii -- enrico.macii@polito.it 14 WP2 (Leader: IFX) TaskDurationPartners Involved T2.1M1-M24 IFX, FHG, SNPS T2.2M1-M24 UNIBO, FHG, SNPS T2.3M1-M24 NXP, ST, SNPS

15. Enrico Macii -- enrico.macii@polito.it 15 WP2 (Leader: IFX)

16. Enrico Macii -- enrico.macii@polito.it 16 WP3 (Leader: POLITO) WP3: Modeling, Simulation and Design of Digital Blocks ­T3.1: Logi-thermal simulation methods and tools Generation of a logic/thermal co-simulator for the target technologies. This simulator will rely on thermal models of the basic design primitives (namely, logic gates, memory elements, interconnects). ­T3.2: Thermal effects in digital circuit design for new CMOS technologies Thermal efficiency comparison of different implementation of a test design using the new technologies and using traditional, state-of-the-art bulk CMOS technologies. ­T3.3: Logic design methodologies for temperature-insensitive circuits Investigation and development of innovative techniques, methodologies and prototype tools for thermal-aware synthesis. ­T3.4: Monitoring circuits and design methodologies for thermal effect compensation Investigation and development of innovative techniques, methodologies and prototype tools for thermal effect compensation, control and management.

17. Enrico Macii -- enrico.macii@polito.it 17 WP3 (Leader: POLITO) TaskDuration Partners Involved T3.1M1-M30 BME, GDA, POLITO, UNIBO T3.2M13-M30IFX, POLITO T3.3M1-M30 POLITO, CSEM, GDA, SNPS, ST T3.4M1-M30 LETI, CSEM, POLITO, GDA, SNPS, ST

18. Enrico Macii -- enrico.macii@polito.it 18 WP3 (Leader: POLITO)

19. Enrico Macii -- enrico.macii@polito.it 19 WP4 (Leader: NXP) WP4: Modeling and Simulation of Analog/RF Blocks ­T4.1: Thermal modeling of analog/RF blocks Since standard compact models, like those developed in the context of WP2, are not sufficient for such components, more accurate behavioral models are needed, which include also self heating effects. Therefore, electrical compact models have to be completed by model parts for the thermal behavior. ­T4.2: Analog/RF circuit analysis in presence of high temperatures and on-chip thermal gradients In this Task, simulation-based methodologies to analyze and reduce the impact of thermal fluctuations on the behavior, yield or reliability of analog/RF blocks will be developed. In a first step, critical analog/RF components will be identified.

20. Enrico Macii -- enrico.macii@polito.it 20 WP4 (Leader: NXP) TaskDurationPartners Involved T4.1M1-M24FHG, NXP, ST, MUN, SNPS, BME. T4.2M7-M30MUN, NXP, ST

21. Enrico Macii -- enrico.macii@polito.it 21 WP4 (Leader: NXP)

22. Enrico Macii -- enrico.macii@polito.it 22 WP5 (Leader: ST) WP5: Modeling and Simulation of Discrete Components ­T5.1: Thermal modeling of discrete components The objective of this task is the investigation and implementation of a modeling framework for discrete components. ­T5.2: Validation of modeling framework for discrete components The main objective of this Task is to validate the modeling framework of Task T5.1 through comparison of the data coming from camera-based analysis to those collected by application of the modeling methodology implemented inside the framework. Validation thus requires the implementation of one or more test cases,

23. Enrico Macii -- enrico.macii@polito.it 23 WP5 (Leader: ST) TaskDurationPartners Involved T5.1M1-M24SNPS, ST, IMEC, UNIBO T5.2M19-M30ST, IMEC, FHG

24. Enrico Macii -- enrico.macii@polito.it 24 WP5 (Leader: ST)

25. Enrico Macii -- enrico.macii@polito.it 25 WP6 (Leader: NXP) WP6: Package/System Modeling and Design Exploration under Ambient Influence ­T6.1: Thermal description of the system package and ambient influence Heat diffusion is a phenomenon where the surrounding ambient has to be considered. This naturally includes the package, as well as the influence from the outside ambient. To to analyze and describe the different thermal systems, measurements and simulations will be performed. The wide range of products of the partners, from discrete components to complex ICs, ensures a good coverage of many applications currently in the market. The thermal characterization will be conducted under different ambient influences and the results will be used as input for modeling the effects of heating. ­T6.2: Thermal distribution in 3D SiP stacks and 2D SoCs While Task T6.1 is focussing on the macroscopic influencing factors as the package structure, this task focuses on describing the local impact of die temperature distribution due to self heating, and the description of thermal feedback. ­T6.3: System-level thermal aware design In this task, thermal design space exploration and automated thermal-aware design capabilities are developed.

26. Enrico Macii -- enrico.macii@polito.it 26 WP6 (Leader: NXP) TaskDurationPartners Involved T6.1M1-M24NXP, ST, SNPS, BME, FHG T6.2M1-M24OFFIS, ST, CV, GDA, IMEC, UNIBO T6.3M1-M30IMEC, ST, CV, OFFIS, UNIBO

27. Enrico Macii -- enrico.macii@polito.it 27 WP6 (Leader: NXP)

28. Validation, Demonstration and Evaluation Activities (WP7)

29. Enrico Macii -- enrico.macii@polito.it 29 WP7 (Leader: NXP) WP7: Validation, Demonstration and Evaluation ­T7.1: Validation of models on test structures I n this task, models developed in other work-packages are validated on multiple test- structures at different levels of abstraction. T7.2: Demonstration of design techniques on test chip In this task, the new design techniques are validated on silicon test structures and test chips. T7.3: Evaluation of prototype tools on test cases In this task, prototype tools are evaluated on the test cases defined in Task T1.3, as well as on additional design examples provided by the industrial partners

30. Enrico Macii -- enrico.macii@polito.it 30 WP7 (Leader: NXP) TaskDurationPartners Involved T7.1M19-M36 IFX, ST, NXP, SNPS, BME, FHG, IMEC, UNIBO T7.2M19-M36 ST, IFX, CSEM, LETI, POLITO, UNIBO T7.3M19-M36 NXP, ST, CV, GDA, MUN, SNPS, BME, IMEC, LETI, OFFIS, POLITO

31. Enrico Macii -- enrico.macii@polito.it 31 WP7 (Leader: NXP)

32. Dissemination, Training, Exploitation and Roadmapping Activities (WP8)

33. Enrico Macii -- enrico.macii@polito.it 33 WP8 (Leader: ST) WP8: Dissemination, Training, Exploitation, Roadmapping ­T8.1: Set-up and maintenance of the project web-site The objective of this Task is the set-up and maintenance of a public web-site that will constitute the main point of collection of the project information, including public deliverables, summary of major scientific achievements advertisement of dissemination and training activities. Maintenance and incremental updates will take place monthly, major revisions and restructuring will occur every six months. ­T8.2: Dissemination The partners of the THERMINATOR Consortium will disseminate the project results through various means. This tasks covers all the dissemination activities. ­T8.3: Training The activities in this task are of two kinds. First, preparation of course material on thermal-aware design. Second, planning, advertisement, organization and execution of the courses. In the first year of the project, existing knowledge and new ideas from all partners will be collected and training material (in electronic form) will be generated by the participants of this task. ­T8.4: Exploitation and Roadmapping The partners of the THERMINATOR Consortium will exploitation the project results through various means. This tasks covers all the dissemination activities.

34. Enrico Macii -- enrico.macii@polito.it 34 WP8 (Leader: ST) TaskDurationPartners Involved T8.1M1-M36ST T8.2M1-M36POLITO, All T8.3M1-M36BME, All T8.4M1-M36 ST, IFX, NXP, CV, GDA, MUN, SNPS, OFFIS, POLITO

35. Enrico Macii -- enrico.macii@polito.it 35 WP8 (Leader: ST)

36. Enrico Macii -- enrico.macii@polito.it 36 WP8 (Leader: ST)