1. Paradigm Shift to 3D and its Impact on our EcoSystem, Standards and EDA Tools Herb Reiter, eda 2 asic Consulting Chairman of GSA EDA Interest Group & 3D IC Working Group EDPS, Monterrey, April 8, 2011

2. Agenda  “2D ICs” make continued innovation very expensive  Need EcoSystem changes to enable many of us to continue innovating  3D demands closer cooperation AND additional standards  Data exchange formats & tools interoperability foster cooperation  Complex assembly processes and much higher packing densities demand more rules (… like living in a condo complex vs on a 50 ac ranch…)  3D technology offers new opportunities for EDA  3D is a SYSTEM integration technology, not limited to IC design  Opens up a wide range of EDA opportunities: -Engage in multi-level modeling -Make proven 2D tools “3D aware” -Solve complex system-level H/W & S/W planning, implementation & verification challenges with EDA tools, flows and methodologies -DFT for economical testing of 3D ICs  Discussion, conclusions, action items

3. Challenges with the proven 2D SoCs 2+ years development time Software is ~ ½ of the TTM NREs of $ 100M and more demand very high volumes to reach breakeven point RISKs: Design error Market changes Competitor moves 1 st Synopsys Keynote, @ LSI, Oct 6, 2010

4. Major Implementation Alternatives Source: eda2asic article in Yole’s 3D Packaging Magazine, Nov 17, 2010

5. 2½ + 3D Commercialization Schedules http://www.i-micronews.com/lectureArticle.asp?id=6351Dr. Phil Garrou, YOLE = this year 2½D with

6.  Characteristics of our current EcoSystem  ICs, packages and PCBs are designed (almost) in isolation  Monolithic “2D ICs” are hitting economical and technical limits  Several modular solutions (PoP, PiP, SiP,… ) are production proven  New 2½D* and 3D configurations are emerging as alternatives to integrate ICs and entire systems (*: 2½D = interposer-based)  What do most of our end customers want ?  Lower cost, smarter, faster, smaller systems with longer battery life  Following latest trends quickly (  shorter time-to-market in design & manuf.)  How can we meet these requirements ?  Architect for 3D implementations (utilize wide I/O, A & D, MEMS, passives ) -Higher level of integration allows reduced power and increased speed -Lots of memory & S/W to increase user friendliness and update systems -IP reuse and modularity to reduce development time and –cost  Add’l standards to simplify cooperation & drive economies of scale  Investments in our design- and manufacturing EcoSystem Semiconductor EcoSystem

7. Cooperation Within the “Food-Chain” Complete Product Package, Interposer, Substrate Wafers OS Appl. S/W Drivers Soft/Hard IP and/or KGD Packaged 3D stacks EDA Design Tools/Flows Foundry contributes: “2D” PDK, die COST, TSV models, TCE data, thermal characteristics, … Materials vendor: COST, Pkg dimension thermal characteristics,… OSAT contributes: COST projections for assembly, test, & shipping. Production test requirements, … Fabless/light vendor: Idea, architecture, targets for COST, Power, Performance, FormFactor, … IP Partner contributes: “2D” license & royalties, models of IP blocks. And for 3D: Licensing & KGD COST, die-level models, … Software Partner: H/W & S/W co-design needs, memory footprint, performance, power dissipation, … EDA can play an essential role in building the 3D EcoSystem!

8. SYSTEM Designers SOFTWARE Designers The Case for Standards in 3D Design CIRCUIT Designers Manufacturers Fab, Assembly, Test Design Rules, Libraries, Models Design Files and Test Programs Design tools Modeling tools Standards for technical hand-off criteria & business responsibilities Standards to express material characteristics & manufacturing capabilities EDA Vendors Interoperability

9. 3D/TSV Modeling & Design Steps “3D” PDK Major 3D design steps to “hand-off” at fabless / fablight silicon vendors 3D System Design and Partitioning 3D-aware IC Layers Implementation Wafer, TSV, Interposer, Passives & Package’s: Electrical, thermal & mechanical characteristics “2D” PDK data and From FABs, OSATs and materials suppliers Standards for modeling and data exchange formats between companies Interoperability between tools Die- & Block- level IP Models 3D-Layers & Stack Verification for Design “hand-off” To Manuf.

10. System Planning & Partitioning Including die-level IP Reuse New EDA Opportunities in 3D EcoSystem H/W Dev. Tools for: S/W Dev. Tools: Operating System. Applications Software. Drivers. Field Updates Verification of new design portion(s) and entire system. Test program development Hand-off to manufacturing Logical & Physical 3D-aware Implementation of new design portion(s)

11. EDA Opportunities in 3D Design  Modeling tools/flows to expand 2D PDKs to “3D PDKs”  Capture electrical-, thermal-, magnetic-, mechanical characteristics,…  Modify proven 2D tools to make them “3D aware”  PI, SI, noise, temp analysis, TSV strain, P & R ?,…  Create tools for 3D specific new challenges  3D DFT, die + stack + I/P + passives + pkg co-design, warpage, magnetics,…  Create system-level H/W planning and partitioning tools  “Pathfinding” for lowest cost, lowest power, smallest formfactor,…  Create system-level hardware and software co-design tools  System partitioning in H/W and S/W, emulating, debugging, updating,… --------------------  Create tools for OS-, appl. S/W-, drivers development & debug  Multi- and many-core, handling of very wide busses, error detection and recovery, managing hardware redundancy (TSVs, memory, logic?, …)

12. A Closer Look at System Design EDA vendors say about system-level tools:  They have to be application specific and utilize a high-level of abstraction to offer significantly higher productivity  Joint development of application-specific tools requires very good cooperation with the actual users at the EDA customers  The number of system designers is much smaller than the number of circuit designers Points above are valid concerns, but keep in mind:  As system complexity and value increase, the need for system-level tools increases beyond C++ to RTL,…  large opportunity for EDA !  Higher abstraction level tools will increase number of system designers  Today’s EDA tools sell per seat for the contract period. Their price is not tied to the value they create  New business model for system tools?  System designers who implement large “2D SoCs” can benefits from 3D system tools as well  increases user base and revenues for these tools !  Systems’ software content is increasing and extends systems’ useful life significantly  Tools for H/W & S/W co-design & S/W development needed!

13. 3D Challenges & Opportunities for EDA Incremental minor model formats Incremental minor DRC decks Minor upgrades of 2D tools to recognize incremental features Standards for Design Exchange Formats Pathfinding tools and estimation methods, to make it worthwhile for users New Biz Model, to make it worthwhile for providers Design Kits include Design Rules DRC/LVS Decks Spice Models DFM Kits Standard physical RTL 2 GDS design tools and flow Private domain of IDMs and system design entities Interface to Manufacturing Physical Design System Design 3D 2D Incremental EDA features and problems associated with migration to 3D Top-down and very broad-brush perspective Key challenges are on the System Design Side of things Source: Riko Radojcic, Qualcomm

14. Discussion Topics  When will 2½D cross the chasm? When will 3D …. ?  Which applications will use 2½D first ? // … 3D/TSVs first ?  Are EDA vendors jumping into the 3D drivers seat ?  How are IDMs vs fabless/fablight vendors approaching 3D ?  Would a different EDA biz model increase support for 3D ?  Can we jointly define open EDA standards for 3D or do we want to wait for de-facto (= proprietary) standards ?  What are bigger opportunities (vs 3D) to grow EDA revenues?  NEXT technologies: 3D monolithic ICs and Carbon Nanotubes

15. herb@eda2asic.com Thank You ! C ooperation S tandards S ystem-level B usiness M odel