1. Module-3 (MOS designs,Stick Diagrams,Designrules)
Sandeep Radhakrishnan
VJEC,Chemperi

2. Before we start…. In this module we are going to study
NMOS and CMOS Design Styles
Both combinational and sequential
(We had done many examples in our class.So Please go on that.Here I am giving the design of basic gates only)
Stick Diagrams
Layouts
Lamda and micron design rules

3. Transistors as Switches
We can view MOS transistors as electrically controlled switches
Voltage at gate controls path from source to drain

4. CMOS Inverter A Y 1

5. CMOS Inverter A Y 1

6. CMOS Inverter A Y 1

7. CMOS NAND Gate A B Y 1

8. CMOS NAND Gate A B Y 1

9. CMOS NAND Gate A B Y 1

10. CMOS NAND Gate A B Y 1

11. CMOS NAND Gate A B Y 1

12. CMOS NOR Gate A B Y 1

13. VLSI design aims to translate circuit concepts onto silicon.
stick diagrams are a means of capturing topography and layer information using simple diagrams.
Stick diagrams convey layer information through colour codes (or monochrome encoding).
Acts as an interface between symbolic circuit and the actual layout.

14. Stick diagrams A stick diagram is a cartoon of a layout.
Does show all components/vias (except possibly tub ties), relative placement.
Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

15. Stick Diagrams Key idea: "Stick figure cartoon" of a layout
Useful for planning layout
relative placement of transistors
assignment of signals to layers
connections between cells
cell hierarchy

16. Stick Diagrams (3/3)

17. Stick Diagrams – Notations
Metal 1
Can also draw
in shades of
gray/line style.
poly
ndiff
pdiff
Similarly for contacts, via, tub etc..

18. Stick Diagrams – Some rules
Rule 1. When two or more ‘sticks’ of the same type cross or touch each other that represents electrical contact.

19. Stick Diagrams – Some rules
Rule 2. When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection explicitly).

20. Stick Diagrams – Some rules
Rule 3. When a poly crosses diffusion it represents a transistor.
Note: If a contact is shown then it is not a transistor.

21. Stick Diagrams – Some rules
Rule 4. In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must lie on one side of the line and all nMOS will have to be on the other side.

22. Stick diagram -> CMOS transistor circuit
Vdd = 5V
Vout
Vdd = 5V
Vin
pMOS
Vin
Vout
nMOS
In practice, first draw stick diagram for nMOS section and analyse (pMOS is dual of nMOS section)

23. Stick Diagrams
Stick Diagrams
Gnd
VDD X
VDD
Gnd

24. Static CMOS NAND gate

25. Static CMOS NOR gate

26. Static CMOS Design Example Layout

27. Draw the stick diagram

28. Identify the Circuit

30. CMOS INVERTER

31. Layout of CMOS NAND

32. Please practice more examples

33. Design Rules

34. Design rules
Circuit engineers needs to reduce the size but process engineers needs a controllable and reproducible fabrication
So we needs design rules to get more yield.
Design rules can never be met exactly at the wafer level because physical nature of semiconductor causes some variations.
Parameter limits that cover six standard deviation
ensure that 99.7 percentage meets the specification.

35. Design Rules
Interface between the circuit designer and process engineer
Guidelines for constructing process masks
Unit dimension: minimum line width
scalable design rules: lambda parameter
absolute dimensions: micron rules
Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur
A complete set includes
set of layers
intra-layer: relations between objects in the same layer
inter-layer: relations between objects on different layers

36. Why Have Design Rules?
To be able to tolerate some level of fabrication errors such as
Mask misalignment
Dust
Process parameters (e.g., lateral diffusion)
Rough surfaces
Motivation for design rules – next slide

37. l Based Design Rules Chips are specified with set of masks
Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design rules
Express rules in terms of l = f/2
E.g. l = 0.3 mm in 0.6 mm process
0: Introduction

38. NMOS Design Rules( based)
Minimum width of PolySi and diffusion line 2
Minimum width of Metal line 3 as metal lines run over a more uneven surface than other conducting layers to ensure their continuity
Metal
Diffusion 3 2 2
Polysilicon

39. Design Rules Metal 2 Diffusion 2 3 Polysilicon
PolySi – PolySi space 2
Metal - Metal space 2
Diffusion – Diffusion 3 To avoid the possibility of their associated regions overlapping and conducting current
Metal 2
Diffusion 2 3
Polysilicon

40. Design Rules Metal Diffusion  Polysilicon Diffusion – PolySi 
Metal lines can pass over both diffusion and polySi without electrical effect. Where no separation is specified, metal lines can overlap or cross
Metal
Diffusion 
Polysilicon

41. Metal Vs PolySi/Diffusion
Metal lines can pass over both diffusion and polySi without electrical effect
It is recommended practice to leave  between a metal edge and a polySi or diffusion line to which it is not electrically connected
Metal 
Polysilicon

42. Depletion Transistor
We need depletion implant
An implant surrounding the Transistor by 2l
Ensures that no part of the transistor remains in the enhancement mode
A separation of 2l from the gate of an
enhancement transistor avoids affecting
the device. 2l

43. Depletion Transistor
Implants are separated by 2l to prevent them from merging 2l

44. Contact Area must be a min. of 2l*2l to ensure adequate contact area.

45. Contact Cut Metal connects to polySi/diffusion by contact cut.
Contact area: 2l*2l
Metal and polySi or diffusion must overlap this contact area by l so that the two desired conductors encompass the contact area despite any mis-alignment between conducting layers and the contact hole 4l

46. Contact Cut Contact cut – any gate: 2l apart
Why? No contact to any part of the gate. 4l 2l

47. Contact Cut Contact cut – contact cut: 2l apart
Why? To prevent holes from merging. 2l

48. Nmos Design rules N+Diffusion Mask Diffusion width 2λ
Diffusion spacing 3λ
Implant Mask
Implant gate overlap 1.5λ
Implant to enhancement gate spacing 1.5λ
Buried contact mask
Buried contact to active device 2λ(to avoid short circuit)
Overlap in diffusion direction 2λ
Overlap in poly or field direction 1λ
Buried contact to unrelated poly or diffusion spacing 2λ

49. Poly Mask
Poly width 2λ
Poly spacing 2λ
Poly diffusion spacing 1λ
Poly gate extension beyond diffusion 2 λ
Diffuin to poly edge 2 λ
Contact Mask
Contact size 2 λ x 2 λ
Contact diffusion overlap 1 λ
Contact poly overlap 1 λ
Contact to contact space 2 λ
Contact to FET channel 2 λ
Contact to metal overlap 1 λ
Metal mask
Metal width 3 λ
Metal spacing 3 λ

50. Rules for CMOS layout
To ensure the separation of the PMOS and NMOS devices,
n-well supporting PMOS is 6l away from the active area of NMOS transistor.
n-well
Why?
Avoids overlap of the associated regions n+ 6l

51. Rules for CMOS layout 2l
N-well must completely surround the PMOS device’s active area by 2l

52. Rules for CMOS layout 2l
The threshold implant mask covers all n-well and surrounds the n-well by l

53. Rules for CMOS layout
The p+ diffusion mask defines the areas to receive a p+ diffusion.
It is coincident with the threshold mask surrounding the PMOS transistor but excludes the n-well region to be connected to the supply. 2l

54. Rules for CMOS layout
A p+ diffusion is required to effect the ground connection to the substrate. Thus mask also defines this substrate region. It surrounds the conducting material of this contact by l. 4

55. Simplified Design Rules
Conservative rules to get you started
0: Introduction

56. Micron rules

58. Intra-Layer Design Rule Origins
Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fab
minimum line width is set by the resolution of the patterning process (photolithography)
Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab
0.3 micron
why would the spacing of the active (n) area be different that drawn? - due to lateral diffusion
0.15
0.3 micron
0.15

59. Intra-Layer Design Rules4
Metal2 3

60. Transistor Layout

61. Select Layer

62. Please refer the text for more details about the design rules….
Text:VLSI Technology
Author:Sujatha Pandey and Manoj Pandey
Page No.:5.36 to 5.44