1. Lecture #23 Page 1 ECE 4110– Sequential Logic Design Lecture #23 Agenda 1.Latches and Flip-Flops Review Announcements 1.HW #11assigned.

2. Lecture #23 Page 2 Latches Latches - we’ve learned all of the VHDL syntax necessary to describe sequential storage elements - Let’s review where sequential devices come from SR Latch - To understand the SR Latch, we must remember the truth table for a NOR GateAB F 00 1 01 0 10 0 11 0

3. Lecture #23 Page 3 Latches SR Latch - when S=0 & R=0, it puts this circuit into a Bi-stable feedback mode where the output is either: Q=0, Qn=1Q=1, Qn=0 AB FAB F 00 1 (U2)00 1 (U1) 01 001 0 (U2) 10 0 (U1)10 0 11 011 0 0 0 0 0 1 11 1 0 0 0 0

4. Lecture #23 Page 4 Latches SR Latch - we can force a known state using S & R: Set (S=1, R=0)Reset (S=0, R=1) AB FAB F 00 1 (U1)00 1 (U2) 01 001 0 (U1) 10 0 (U2)10 0 11 0 (U2)11 0 (U1) 1 1 0 1 0 00 0 1 0 1 1

5. Lecture #23 Page 5 Latches SR Latch - we can write a Truth Table for an SR Latch as follows S RQ Qn. 0 0Last QLast Qn - Hold 0 10 1 - Reset 1 01 0 - Set 1 10 0 - Don’t Use - S=1 & R=1 forces a 0 on both outputs. However, when the latch comes out of this state it is metastable. This means the final state is unknown.

6. Lecture #23 Page 6 Latches S’R’ Latch - we can also use NAND gates to form an inverted SR Latch S’ R’Q Qn. 0 01 1- Don’t Use 0 11 0 - Set 1 00 1 - Reset 1 1 Last Q Last Qn - Hold

7. Lecture #23 Page 7 Latches SR Latch w/ Enable - we then can add an enable line using NAND gates - remember the Truth Table for a NAND gate AB F 00 1 - a 0 on any input forces a 1 on the output 01 1 - when C=0, the two EN NAND Gate outputs are 1, which forces “Last Q/Qn” 10 1 - when C=1, S & R are passed through INVERTED 11 0

8. Lecture #23 Page 8 Latches SR Latch w/ Enable - the truth table then becomes C S RQ Qn. 1 0 0Last Q Last Qn - Hold 1 0 10 1 - Reset 1 1 01 0 - Set 1 1 1 1 1 - Don’t Use 0 x x Last Q Last Qn - Hold

9. Lecture #23 Page 9 Latches D Latch - a modification to the SR Latch where R = S’ creates a D-latch - when C=1, Q <= D - when C=0, Q <= Last Value C DQ Qn. 1 00 1- track 1 11 0 - track 0 xLast Q Last Qn - Hold

10. Lecture #23 Page 10 Latches VHDL of a D Latch architecture Dlatch_arch of Dlatch is begin LATCH : process (D,C,Q) begin if (C=‘1’) then Q<=D; Qn<=not D; else Q<=Q; Qn<=Qn; end if; end process; end architecture;

11. Lecture #23 Page 11 Flip Flops D-Flip-Flops - we can combine D-latches to get an edge triggered storage device (or flop) - the first D-latch is called the “Master”, the second D-latch the “Slave” Master Slave CLK=0, Q<=D “Open”CLK=0, Q<=Q “Close” CLK=1, Q<=Q “Closed”CLK=1, Q<=D “Open” - on a rising edge of clock, D is “latched” and held on Q until the next rising edge

12. Lecture #23 Page 12 Flip Flops VHDL of a D-Flip-Flop architecture DFF_arch of DFF is begin FLOP : process (CLK) begin if (CLK’event and CLK=1) then -- recognized by all synthesizers as DFF Q<=D; Qn<=not D; else Q<=Q; Qn<=Qn; end if; end process; end architecture;