1. Chapter 5 Synchronous Sequential Logic 授課教師 : 張傳育 博士 (Chuan-Yu Chang Ph.D.) E-mail: chuanyu@yuntech.edu.twchuanyu@yuntech.edu.tw Tel: (05)5342601 ext. 4337 Office: EB212

2. Digital Circuits 5-2 5-1 Introduction Combinational circuits contains no memory elements the outputs depends on the inputs

3. Digital Circuits 5-3 5-2 Sequential Circuits ■ Sequential circuits Sequential circuits consist of a feedback path The binary information stored in these elements at any given time defines the state of the sequential circuit (inputs, current state)  (outputs, next state) synchronous: the transition happens at discrete instants of time asynchronous: at any instant of time

4. Digital Circuits 5-4 Synchronous sequential circuits a master-clock generator to generate a periodic train of clock pulses the clock pulses are distributed throughout the system Also called clocked sequential circuits most commonly used no instability problems the memory elements: flip-flops binary cells capable of storing one bit of information two outputs: one for the normal value and one for the complement value maintain a binary state indefinitely until directed by an input signal to switch states 5-2 Sequential Circuits (cont.)

5. Digital Circuits 5-5 Fig. 5.2 Synchronous clocked sequential circuit 5-2 Sequential Circuits (cont.) 多了時脈訊號

6. Digital Circuits 5-6 5-3 Latches Latches Storage elements that operate with single level. level sensitive devices Flip-Flops Controlled by a clock transition. Edge sensitive devices

7. Digital Circuits 5-7 5-3 Latches Basic flip-flop circuit two NOR gates more complicated types can be built upon it directed-coupled RS flip-flop: the cross-coupled connection an asynchronous sequential circuit (S,R)= (0,0): no operation (S,R)=(0,1): reset (Q=0, the clear state) (S,R)=(1,0): set (Q=1, the set state) (S,R)=(1,1): indeterminate state (Q=Q'=0)

8. Digital Circuits 5-8 SR latch with NAND gates Fig. 5.4 SR latch with NAND gates 5-3 Latches (cont.)

9. Digital Circuits 5-9 SR latch with control input E n =0, no change E n =1, information from the S or R input is allowed to affect the latch. Fig. 5.5 SR latch with control input 5-3 Latches (cont.) The set state is reached with En=1, S=1, R=0 To change to the reset state, En=1, S=0, R=1 When En=0, the circuit remains in its current state. An indeterminate condition occurs when all three inputs are equal to 1 S- R-

10. Digital Circuits 5-10 D Latch eliminate the undesirable conditions of the indeterminate state in the RS flip-flop D: data gated D-latch D  Q when E n =1; no change when E n =0 Fig. 5.6 D latch S_ R_ 0/1 1/D' 1/D 5-3 Latches (cont.)

11. Digital Circuits 5-11 Fig. 5.7 Graphic symbols for latches 5-3 Latches (cont.) 當 NAND gate 的輸入端為 1 時，輸出的狀態由另一個輸 入端決定。 當 NAND gate 的輸入端為 0 時，輸出端必為 1 。 因此， NAND gate 屬於低態動作 (active low) 。所以在輸入端 加上小圈圈。 NOR 組成之 RS Flip-Flop NAND 組成之 RS Flip-Flop

12. Digital Circuits 5-12 5-4 Flip-Flops A trigger The state of a latch or flip-flop is switched by a change of the control input Level triggered – latches Edge triggered – flip-flops Fig. 5.8 Clock response in latch and flip-flop

13. Digital Circuits 5-13 If level-triggered flip-flops are used the feedback path may cause instability problem To solve the instability problem Master-Slave Flip-Flops Edge-triggered flip-flops the state transition happens only at the edge eliminate the multiple-transition problem 5-4 Flip-Flops (cont.)

14. Digital Circuits 5-14 Edge-triggered D flip-flop Master-slave D flip-flop two separate flip-flops a master flip-flop (positive-level triggered) a slave flip-flop (negative-level triggered) Fig. 5.9 Master-slave D flip-flop Clk =0, slave D latch Enable, Q=Y master D latch Disable Clk =1, master D latch Enable, Y=D slave D latch Disable, Q=Y Clk =0, slave D latch Enable, Q=D master D latch disable

15. Digital Circuits 5-15 CP = 1: (S,R)  (Y,Y'); (Q,Q') holds CP = 0: (Y,Y') holds; (Y,Y')  (Q,Q') (S,R) could not affect (Q,Q') directly the state changes coincide with the negative-edge transition of CP 第三版內容，參考用 !

16. Digital Circuits 5-16 Edge-triggered flip-flops the state changes during a clock-pulse transition A D-type positive-edge-triggered flip-flop Fig. 5.10 D-type positive-edge- triggered flip-flop When Clk =0, S and R are maintained at the logic-1 level. => 輸出維持現態。 Clk=1, D=0 => R=0, => Q=0

17. Digital Circuits 5-17 three basic flip-flops (S,R) = (0,1): Q = 1 (S,R) = (1,0): Q = 0 (S,R) = (1,1): no operation (S,R) = (0,0): should be avoided Fig. 5.10 D-type positive-edge- triggered flip-flop

18. Digital Circuits 5-18 1 0 1 第三版內容， 參考用 !

19. Digital Circuits 5-19 The setup time D input must be maintained at a constant value prior to the application of the positive Clk pulse = the propagation delay through gates 4 and 1 data to the internal latches The hold time D input must not changes after the application of the positive Clk pulse = the propagation delay of gate 3 clock to the internal latch The propagation delay time The interval between the trigger edge and the stabilization of the output to a new state.

20. Digital Circuits 5-20 Summary Clk =0: (S,R) = (1,1), no state change Clk =  : state change once Clk =1: state holds eliminate the feedback problems in sequential circuits All flip-flops must make their transition at the same time

21. Digital Circuits 5-21 Other Flip-Flops The edge-triggered D flip-flops The most economical and efficient Positive-edge and negative-edge Fig. 5.11 Graphic symbols for edge- triggered D flip-flop

22. Digital Circuits 5-22 JK flip-flop D=JQ'+K'Q J=0, K=0 : D=Q, no change J=0, K=1: D=0  Q =0 J=1, K=0: D=1  Q =1 J=1, K=1: D=Q'  Q =Q' Fig. 5.12 JK flip-flop

23. Digital Circuits 5-23 T flip-flop D = T ⊕ Q = TQ'+T'Q T=0: D=Q, no change T=1: D=Q'  Q=Q' Fig. 5.13 T flip-flop

24. Digital Circuits 5-24 Characteristic tables

25. Digital Circuits 5-25 Characteristic equations D flip-flop Q ( t +1) = D JK flip-flop Q ( t +1) = JQ'+K'Q T flop-flop Q ( t +1) = T ⊕ Q

26. Digital Circuits 5-26 Direct inputs asynchronous set and/or asynchronous reset S_ reset_ Fig. 5.14 D flip-flop with asynchronous reset

27. Digital Circuits 5-27 5-5 Analysis of Clocked Sequential Circuits A sequential circuit Clocked sequential circuit (inputs, current state)  (output, next state) 推得 a state transition table or state transition diagram Fig. 5.15 Example of sequential circuit

28. Digital Circuits 5-28 State equations A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A'(t)x(t) A compact form A ( t+1 ) = Ax + Bx B ( t+1 ) = A’x The output equation y ( t ) = ( A ( t )+ B ( t )) x '( t ) y = ( A+B ) x '

29. Digital Circuits 5-29 State table State transition table = state equations

30. Digital Circuits 5-30 State equation A(t + 1) =Ax + Bx B(t + 1) = Ax y = Ax + Bx 由 Table 5.2 ，以卡諾圖畫簡可得 state equation State Table 也可表示成下表

31. Digital Circuits 5-31 State diagram State transition diagram a circle: a state a directed lines connecting the circles: the transition between the states Each directed line is labeled 'inputs/outputs‘ a logic diagram  a state table  a state diagram Fig. 5.16 State diagram of the circuit of Fig. 5.15

32. Digital Circuits 5-32 Flip-flop input equations Flip-flop input equation The part of circuit that generates the inputs to flip- flops Also called excitation functions D A = Ax +Bx D B = A'x The output equations The part of the combinational circuit that generates external outputs is described algebraically by a set of Boolean functions to fully describe the sequential circuit y = (A+B)x'

33. Digital Circuits 5-33 Analysis with D flip-flops The input equation D A = A ⊕ x ⊕ y The state equation A ( t+1 )= A ⊕ x ⊕ y Fig. 5.17 Sequential circuit with D flip-flop

34. Digital Circuits 5-34 Analysis with JK flip-flops Determine the flip-flop input function in terms of the present state and input variables Used the corresponding flip-flop characteristic table to determine the next state Fig. 5.18 Sequential circuit with JK flip-flop

35. Digital Circuits 5-35 J A = B, K A = Bx' J B = x', K B = A'x + Ax’ derive the state table Or, derive the state equations using characteristic eq. Analysis with JK flip-flops (cont.)

36. Digital Circuits 5-36 State transition diagram Fig. 5.19 State diagram of the circuit of Fig. 5.18 State equation for A and B: Analysis with JK flip-flops (cont.)

37. Digital Circuits 5-37 Analysis with T flip-flops The characteristic equation Q ( t+1 )= T ⊕ Q = TQ'+T'Q Fig. 5.20 Sequential circuit with T flip-flop

38. Digital Circuits 5-38 Analysis with T flip-flops (cont.) The input and output functions T A =Bx T B = x y = AB The state equations A(t+1) = (Bx)'A+(Bx)A' =AB'+Ax'+A'Bx B ( t+1 ) = x ⊕ B

39. Digital Circuits 5-39 State Table Analysis with T flip-flops (cont.)

40. Digital Circuits 5-40 Mealy and Moore models The Mealy model: the outputs are functions of both the present state and inputs (Fig. 5-15) the outputs may change if the inputs change during the clock pulse period the outputs may have momentary false values unless the inputs are synchronized with the clocks The Moore model: the outputs are functions of the present state only (Fig. 5-18, 5-20) The outputs are synchronous with the clocks

41. Digital Circuits 5-41 Mealy and Moore models (cont.) Fig. 5.21 Block diagram of Mealy and Moore state machine

42. Digital Circuits 5-42 5-7 State Reduction and Assignment State Reduction reductions on the number of flip-flops and the number of gates a reduction in the number of states may result in a reduction in the number of flip-flops a example state diagram Fig. 5.25 State diagram

43. Digital Circuits 5-43 state a a b c d e f f g f g a input0 1 0 1 0 1 1 0 1 0 0 output0 0 0 0 0 1 1 0 1 0 0 only the input-output sequences are important two circuits are equivalent have identical outputs for all input sequences the number of states is not important Fig. 5.25 State diagram

44. Digital Circuits 5-44 Equivalent states Two states are said to be equivalent for each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state one of them can be removed

45. Digital Circuits 5-45 Reducing the state table e=g d=? ( 狀態 g 已經被狀態 e 所取代 )

46. Digital Circuits 5-46 the reduced finite state machine statea a b c d e d d e d e a input0 1 0 1 0 1 1 0 1 0 0 output0 0 0 0 0 1 1 0 1 0 0 ( 狀態 f 已經被狀態 d 所取代 )

47. Digital Circuits 5-47 the checking of each pair of states for possible equivalence can be done systematically (9-5) the unused states are treated as don't-care condition  fewer combinational gates Fig. 5.26 Reduced State diagram

48. Digital Circuits 5-48 State assignment to minimize the cost of the combinational circuits three possible binary state assignments

49. Digital Circuits 5-49 State assignment any binary number assignment is satisfactory as long as each state is assigned a unique number use binary assignment 1

50. Digital Circuits 5-50 5-8 Design Procedure From the word description of the circuit behavior, derive a state diagram for the circuit. State reduction if necessary Assign binary values to the states Obtain the binary-coded state table Choose the type of flip-flops Derive the simplified flip-flop input equations and output equations Draw the logic diagram

51. Digital Circuits 5-51 Synthesis using D flip-flops An example state diagram and state table Detects a sequence of three or more consecutive 1’s in a string of bits coming through an input line. Fig. 5.27 State diagram for sequence detector

52. Digital Circuits 5-52 The flip-flop input equations A(t+1) = D A (A,B,x) =  (3,5,7) B(t+1) = D B (A,B,x) =  (1,5,7) The output equation y(A,B,x) =  (6,7) Logic minimization using the K map D A = Ax + Bx D B = Ax + B'x y = AB Synthesis using D flip-flops

53. Digital Circuits 5-53 Fig. 5.28 Maps for sequence detector

54. Digital Circuits 5-54 Sequence detector The logic diagram Fig. 5.29 Logic diagram of sequence detector

55. Digital Circuits 5-55 Excitation tables A state diagram  flip-flop input functions straightforward for D flip-flops we need excitation tables for JK and T flip-flops

56. Digital Circuits 5-56 Synthesis using JK flip-flops The state table and JK flip-flop inputs

57. Digital Circuits 5-57 J A = Bx'; K A = Bx J B = x; K B = (A ⊕ x)‘ y = ? Fig. 5.30 Maps for J and K input equations

58. Digital Circuits 5-58 Fig. 5.31 Logic diagram for sequential circuit with JK flip-flops

59. Digital Circuits 5-59 Synthesis using T flip-flops A n -bit binary counter the state diagram no inputs (except for the clock input) Fig. 5.32 State diagram of three- bit binary counter

60. Digital Circuits 5-60 The state table and the flip-flop inputs

61. Digital Circuits 5-61 Fig. 5.33 Maps of three-bit binary counter

62. Digital Circuits 5-62 Logic simplification using the K map T A2 = A 1 A 2 T A1 = A 0 T A0 = 1 The logic diagram Fig. 5.34 Logic diagram of three-bit binary counter

63. Digital Circuits 5-63 5-7 Synthesizable HDL Models of Sequential Circuits Behavioral Modeling Example: Two ways to provide free-running clock Example: Another way to describe free-running clock

64. Digital Circuits 5-64 Behavioral Modeling  always statement Examples: Two procedural blocking assignments:Two nonblocking assignments:

65. Digital Circuits 5-65 Flip-Flops and Latches ■ HDL Example 5.1

66. Digital Circuits 5-66 Flip-Flops and Latches ■ HDL Example 5.2

67. Digital Circuits 5-67 Characteristic Equation Q(t + 1) = Q ⊕ T Q(t + 1) = JQ + KQ For a T flip-flop For a JK flip-flop ■ HDL Example 5.3

68. Digital Circuits 5-68 HDL Example 5-3 (Continued)

69. Digital Circuits 5-69 HDL Example 5-4  Functional description of JK flip-flop

70. Digital Circuits 5-70 State Diagram ■ HDL Example 5.5: Mealy HDL model

71. Digital Circuits 5-71 HDL Example 5-5 (Continued)

72. Digital Circuits 5-72 HDL Example 5-5 (Continued)

73. Digital Circuits 5-73 Mealy_Zero_Detector Fig. 5.22 Simulation output of Mealy_Zero_Detector

74. Digital Circuits 5-74 HDL Example 5-6: Moore Model FSM

75. Digital Circuits 5-75 Simulation Output of HDL Example 5-6 Fig. 5.23 Simulation output of HDL Example 5.6

76. Digital Circuits 5-76 Structural Description of Clocked Sequential Circuits ■ HDL Example 5.7: State-diagram-based model

77. Digital Circuits 5-77 HDL Example 5-7 (Continued)

78. Digital Circuits 5-78 HDL Example 5-7 (Continued)

79. Digital Circuits 5-79 HDL Example 5-7 (Continued)

80. Digital Circuits 5-80 HDL Example 5-7 (Continued)

81. Digital Circuits 5-81 Simulation Output of HDL Example 5-7 Fig. 5.24 Simulation output of HDL Example 5.7