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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic SEQUENTIAL LOGIC
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Positive Feedback: Bi-Stability
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Meta-Stability Gain should be larger than 1 in the transition region
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic SR-Flip Flop Q S R Q S R Q Q 1 0 1 0 1 1 0 0 Q 1 0 1 Q 0 1 1 Q Q
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic JK- Flip Flop
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Other Flip-Flops
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Race Problem
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Master-Slave Flip-Flop
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Propagation Delay Based Edge-Triggered
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Edge Triggered Flip-Flop
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Flip-Flop: Timing Definitions
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Maximum Clock Frequency
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic CMOS Clocked SR- FlipFlop
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Flip-Flop: Transistor Sizing
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic 6 Transistor CMOS SR-Flip Flop
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Charge-Based Storage
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Master-Slave Flip-Flop
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic 2 phase non-overlapping clocks
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic 2-phase dynamic flip-flop
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Flip-flop insensitive to clock overlap
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic C 2 MOS avoids Race Conditions
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Pipelining
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Pipelined Logic using C 2 MOS
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Example
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic NORA CMOS Modules
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Doubled C 2 MOS Latches
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic TSPC - True Single Phase Clock Logic
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Digital Integrated Circuits© Prentice Hall 1995 Sequential Logic Master-Slave Flip-flops
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