2. Objectives: Given input logice levels, state the output of an RS NAND and RS NOR. Given a clock signal, determine the PGT and NGT. Define “Edge Triggered” and “Level Triggered”. Draw a Clocked F/F with and “Edge Triggered” clock input and a “Level Triggered” clock input.

3. Logic circuits are classified into two groups: Combinational logic circuits Sequential logic circuits Basic building blocks include: Basic building blocks include FLIP-FLOPS: LOGIC CIRCUITS Logic gates make decisions Flip Flops have memory

4. FLIP-FLOPS Memory device capable of storing one bit Memory means circuit remains in one state after condition that caused the state is removed. Two outputs designated Q and Q-Not that are always opposite or complimentary. When referring to the state of a flip flop, referring to the state of the Q output.

5. FLIP-FLOPS To SET a flip flop means to make Q =1 To RESET a flip flop means to make Q = 0 Symbol Truth Table SET RESET

6. FLIP-FLOPS The flip flop is a bi-stable multivibrator; it has two stable states. The RS flip flop can be implemented with transistors.

7. R-S FLIP-FLOP Symbols: Truth Table: Set Reset S R Q Q Normal Comple- mentary FF Mode of Operation Inputs Outputs S R Q Q’ Prohibited0 0 1 1 Set0 1 1 0 Reset1 0 0 1 Hold1 1 Q Q’ NOTE: Active-LOW inputs

8. R-S FLIP-FLOP Active-Low NAND LATCH DEMORGANIZED NAND LATCH

9. ACTIVE-LOW R-S FLIP-FLOP TIMING DIAGRAMS

10. R-S FLIP-FLOP Active-High

11. ACTIVE-HIGH R-S FLIP-FLOP TIMING DIAGRAMS

12. 1. Logic gates make decisions, flip flops have ____________________? 2. One flip flop can store how many bits? 3. What are the two outputs of a flip flop? 4. When referring to the state of a flip flop, we’re referring to the state of which output? 5. What does it mean to SET a flip flop? 6. What does it mean to RESET a flip flop? TEST Memory 1 QQ-NOT Q Q = 1 Q = 0

13. What is the mode of operation of the R-S flip-flop (set, reset or hold)? What is the output at Q from the R-S flip-flop (active LOW inputs)? Mode of operation = ? ? H L Low Reset TEST Mode of operation = ? ? L H ? H H High Hold Set

14. CLOCKED R-S FLIP-FLOP Set Reset S R Q Q FF ASYNCHRONOUS Outputs of logic circuit can change state anytime one or more input changes Set Reset S R Q Q FF Clock CLK SYNCHRONOUS Clock signal determines exact time at which any output can change state

15. Astable multivibrator Clock Digital signal in the form of a rectangular or square wave A clocked flip flop changes state only when permitted by the clock signal

16. TRIGGERING OF FLIP-FLOPS Level-triggering is the transfer of data from input to output of a flip-flop anytime the clock pulse is proper voltage level. Edge-triggering is the transfer of data from input to output of a flip-flop on the rising edge (L-to-H) or falling edge (H-to-L) of the clock pulse. Edge triggering may be either positive-edge (L-to-H) or negative-edge (H-to-L). Level triggering Positive-edge triggering Negative-edge triggering HLHL time NGT-Negative Going Transition PGT-Positive Going Transition

17. CLOCKED R-S FLIP-FLOP Symbols: Truth Table: Mode of operation Inputs Outputs Clk S R Q Q’ Hold + pulse 0 0 no change Reset + pulse 0 1 0 1 Set + pulse 1 0 1 0 Prohibited 1 1 0 0 NOTE: Active-High inputs Set Reset S R Q Q Normal Comple- mentary FF Clock CLK

18. What is the mode of operation of the clocked R-S flip-flop (set, reset, hold)? What is the output at Q from the clocked R-S flip-flop (active HIGH inputs)? H^LH^L Mode of operation = ? ? L^LL^L ? L^HL^H ? High Set High Low Hold Reset TEST

19. CLOCKED R-S FLIP-FLOP TIMING DIAGRAMS

20. POSITIVE EDGE TRIGGERED R-S FLIP-FLOP Symbols: Truth Table:

21. POSITIVE EDGE TRIGGERED R-S FLIP-FLOP TIMING DIAGRAMS

22. NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP Symbols: Truth Table: EDGE DETECTOR

23. NEGATIVE EDGE TRIGGERED R-S FLIP-FLOP TIMING DIAGRAMS

24. TEST 1. Type of flip flop where the outputs of circuit can change state anytime one or more input changes? ASYNCHRONOUS 2. Type of flip flop where the clock signal controls when any output can change state? SYNCHRONOUS 3. What do we call a digital signal in the form of a repetitive pulse or square wave? CLOCK 4. Which is easier to design and troubleshoot, clocked or not clocked flip flops? Clocked flip flops are easier to troubleshoot because we can stop the clock and examine one set of input and output conditions.