1. CSE477 L17 Static Sequential Logic.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 17: Static Sequential Circuits Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477www.cse.psu.edu/~mji www.cse.psu.edu/~cg477 [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

2. CSE477 L17 Static Sequential Logic.2Irwin&Vijay, PSU, 2003 Review: How to Choose a Logic Style  Must consider ease of design, robustness (noise immunity), area, speed, power, system clocking requirements, fan-out, functionality, ease of testing Style# TransEaseRatioed?DelayPower Comp Static81no31 CPL*12 + 22no43 domino6 + 24no22 + clk DCVSL*103yes14 4-input NAND * Dual Rail  Current trend is towards an increased use of complementary static CMOS: design support through DA tools, robust, more amenable to voltage scaling.

3. CSE477 L17 Static Sequential Logic.3Irwin&Vijay, PSU, 2003 A time was probably coming when components would operate so quickly that the distance that signals had to travel would intimately affect the speed of most commercial computers. Then miniaturization and speed would become more nearly synonymous. The Soul of a New Machine, Kidder, pg. 160

4. CSE477 L17 Static Sequential Logic.4Irwin&Vijay, PSU, 2003 Sequential Logic Combinational Logic clock Outputs State Registers Next State Current State Inputs

5. CSE477 L17 Static Sequential Logic.5Irwin&Vijay, PSU, 2003 Timing Metrics clock In Out data stable output stable output stable time clock D Q In Out t su t hold t c-q

6. CSE477 L17 Static Sequential Logic.6Irwin&Vijay, PSU, 2003 System Timing Constraints Combinational Logic clock Outputs State Registers Next State Current State Inputs T  t c-q + t plogic + t su t cdreg + t cdlogic  t hold T (clock period)

7. CSE477 L17 Static Sequential Logic.7Irwin&Vijay, PSU, 2003 Static vs Dynamic Storage  Static storage l preserve state as long as the power is on l have positive feedback (regeneration) with an internal connection between the output and the input l useful when updates are infrequent (clock gating)  Dynamic storage l store state on parasitic capacitors l only hold state for short periods of time (milliseconds) l require periodic refresh l usually simpler, so higher speed and lower power

8. CSE477 L17 Static Sequential Logic.8Irwin&Vijay, PSU, 2003 Latches vs Flipflops  Latches l level sensitive circuit that passes inputs to Q when the clock is high (or low) - transparent mode l input sampled on the falling edge of the clock is held stable when clock is low (or high) - hold mode  Flipflops (edge-triggered) l edge sensitive circuits that sample the inputs on a clock transition -positive edge-triggered: 0  1 -negative edge-triggered: 1  0 l built using latches (e.g., master-slave flipflops)

9. CSE477 L17 Static Sequential Logic.9Irwin&Vijay, PSU, 2003 Positive and Negative Latches clock D Q In Out clock D Q In Out clk Out In clk Out In

10. CSE477 L17 Static Sequential Logic.10Irwin&Vijay, PSU, 2003 Review: The Regenerative Property If the gain in the transient region is larger than 1, only A and B are stable operation points. C is a metastable operation point. A V i2 V o2 V i1 = V o2 V i2 = V o1 B C V o1 V i1 cascaded inverters

11. CSE477 L17 Static Sequential Logic.11Irwin&Vijay, PSU, 2003 Bistable Circuits  The cross-coupling of two inverters results in a bistable circuit (a circuit with two stable states)  Have to be able to change the stored value by making A (or B) temporarily unstable by increasing the loop gain to a value larger than 1 l done by applying a trigger pulse at V i1 or V i2 l the width of the trigger pulse need be only a little larger than the total propagation delay around the loop circuit (twice the delay of an inverter)  Two approaches used l cutting the feedback loop (mux based latch) l overpowering the feedback loop (as used in SRAMs) V i1 V i2

12. CSE477 L17 Static Sequential Logic.12Irwin&Vijay, PSU, 2003 Review (from CSE 271): SR Latch SRQ!Q 00Q memory 1010set 0101reset 1100disallowed S R Q !Q

13. CSE477 L17 Static Sequential Logic.13Irwin&Vijay, PSU, 2003 Review (from CSE 271): Clocked D Latch clock D Latch QD D Q !Q clock transparent mode hold mode

14. CSE477 L17 Static Sequential Logic.14Irwin&Vijay, PSU, 2003 MUX Based Latches Q D clk 0 1 Positive Latch Q D clk 1 0 Negative Latch Q = !clk & Q | clk & D Q = clk & Q | !clk & D feedback transparent when the clock is low transparent when the clock is high feedback  Change the stored value by cutting the feedback loop

15. CSE477 L17 Static Sequential Logic.15Irwin&Vijay, PSU, 2003 TG MUX Based Latch Implementation Q D clk !clk clk input sampled (transparent mode) feedback (hold mode) clk D Latch QD

16. CSE477 L17 Static Sequential Logic.16Irwin&Vijay, PSU, 2003 PT MUX Based Latch Implementation Q D clk!Q !clk clk input sampled (transparent mode) feedback (hold mode)  Reduced area and clock load, but a threshold drop at output of pass transistors so reduced noise margins and performance

17. CSE477 L17 Static Sequential Logic.17Irwin&Vijay, PSU, 2003 Latch Race Problem Combinational Logic clk State Registers clk BB’ Two-sided clock constraint T  t c-q + t plogic + t su T high  t c-q + t cdlogic B Which value of B is stored?

18. CSE477 L17 Static Sequential Logic.18Irwin&Vijay, PSU, 2003 Master Slave Based ET Flipflop QMQM D0 1Q 1 0 Slave Master QMQM D clk 0 1Q 1 0 Slave Master clk QMQM Q D clock D FF QD clk = 0 transparent hold clk = 0  1 hold transparent

19. CSE477 L17 Static Sequential Logic.19Irwin&Vijay, PSU, 2003 MS ET Implementation Q D clk QMQM I1I1 I2I2 I3I3 I4I4 I5I5 I6I6 T2T2 T1T1 T3T3 T4T4 Master Slave!clk clk

20. CSE477 L17 Static Sequential Logic.20Irwin&Vijay, PSU, 2003 MS ET Implementation Q D clk QMQM I1I1 I2I2 I3I3 I4I4 I5I5 I6I6 T2T2 T1T1 T3T3 T4T4 Master Slave!clk clk master transparent slave hold master hold slave transparent

21. CSE477 L17 Static Sequential Logic.21Irwin&Vijay, PSU, 2003 MS ET Timing Properties  Assume propagation delays are t pd_inv and t pd_tx, that the contamination delay is 0, and that the inverter delay to derive !clk is 0  Set-up time - time before rising edge of clk that D must be valid  Propagation delay - time for Q M to reach Q  Hold time - time D must be stable after rising edge of clk -

22. CSE477 L17 Static Sequential Logic.22Irwin&Vijay, PSU, 2003 MS ET Timing Properties  Assume propagation delays are t pd_inv and t pd_tx, that the contamination delay is 0, and that the inverter delay to derive !clk is 0  Set-up time - time before rising edge of clk that D must be valid  Propagation delay - time for Q M to reach Q  Hold time - time D must be stable after rising edge of clk t su = 3 * t pd_inv + t pd_tx t c-q = t pd_inv + t pd_tx t hold = zero

23. CSE477 L17 Static Sequential Logic.23Irwin&Vijay, PSU, 2003 Set-up Time Simulation Volts Time (ns) D clk Q QMQM I 2 out t su = 0.21 ns works correctly t setup

24. CSE477 L17 Static Sequential Logic.24Irwin&Vijay, PSU, 2003 Set-up Time Simulation Volts Time (ns) D clk Q QMQM I 2 out t su = 0.20 ns fails t setup

25. CSE477 L17 Static Sequential Logic.25Irwin&Vijay, PSU, 2003 Propagation Delay Simulation Volts Time (ns) t c-q(LH) = 160 psec t c-q(HL) = 180 psect c-q(LH) t c-q(HL)

26. CSE477 L17 Static Sequential Logic.26Irwin&Vijay, PSU, 2003 Power PC Flipflop D Q !clk clk !clk 0 1 1 01 clk

27. CSE477 L17 Static Sequential Logic.27Irwin&Vijay, PSU, 2003 Power PC Flipflop D Q !clk clk !clk 0 1 1 01 clk master transparent slave hold master hold slave transparent 00 11 00 11

28. CSE477 L17 Static Sequential Logic.28Irwin&Vijay, PSU, 2003 Reduced Load MS ET FF !clkclk Q D !clkclk I1I1 I2I2 I4I4 I3I3 QMQM T2T2 T1T1 reverse conduction  Clock load per register is important since it directly impacts the power dissipation of the clock network.  Can reduce the clock load (at the cost of robustness) by making the circuit ratioed l to switch the state of the master, T 1 must be sized to overpower I 2 l to avoid reverse conduction, I 4 must be weaker than I 1

29. CSE477 L17 Static Sequential Logic.29Irwin&Vijay, PSU, 2003 Non-Ideal Clocks 1-1 overlap 0-0 overlap !clk clk Ideal clocks !clk clk Non-ideal clocks clock skew

30. CSE477 L17 Static Sequential Logic.30Irwin&Vijay, PSU, 2003 Example of Clock Skew Problems D clk X !clk !Q !clkQ clk B A P1P1 P2P2 P3P3 P4P4 I1I1 I2I2 I3I3 I4I4 Race condition – direct path from D to Q during the short time when both clk and !clk are high (1-1 overlap) Undefined state – both B and D are driving A when clk and !clk are both high Dynamic storage – when clk and !clk are both low (0-0 overlap)

31. CSE477 L17 Static Sequential Logic.31Irwin&Vijay, PSU, 2003 Pseudostatic Two-Phase ET FF D clk1 X clk2 !Q clk2Q clk1 B A P1P1 P2P2 P3P3 P4P4 I1I1 I2I2 I3I3 I4I4 clk2 clk1 master transparent slave hold master hold slave transparent dynamic storage t non_overlap

32. CSE477 L17 Static Sequential Logic.32Irwin&Vijay, PSU, 2003 Two Phase Clock Generator clk clk1 clk2 A clk A B B clk1 clk2

33. CSE477 L17 Static Sequential Logic.33Irwin&Vijay, PSU, 2003 Ratioed CMOS Clocked SR Latch 1 1 0 0 onoff on off on M1 S R clk !Q Q M2 M3 M4 M5 M6 M7 M8

34. CSE477 L17 Static Sequential Logic.34Irwin&Vijay, PSU, 2003 Ratioed CMOS Clocked SR Latch 1 1 0 0 onoff off  on  0 1  on off on  on  off M1 S R clk !Q Q M2 M3 M4 M5 M6 M7 M8 0  1

35. CSE477 L17 Static Sequential Logic.35Irwin&Vijay, PSU, 2003 Sizing Issues W/L 5and6 !Q (Volts) W/L 2and4 = 1.5  m/0.25  m W/L 1and3 = 0.5  m/0.25  m so W/L 5and6 > 3

36. CSE477 L17 Static Sequential Logic.36Irwin&Vijay, PSU, 2003 Transient Response Q & !Q (Volts) SET !Q Q Time (ns) t c-!Q t c-Q

37. CSE477 L17 Static Sequential Logic.37Irwin&Vijay, PSU, 2003 6 Transistor CMOS SR Latch clk S R M1 S R clk !Q Q M2 M3 M4 M5 M6 clk

38. CSE477 L17 Static Sequential Logic.38Irwin&Vijay, PSU, 2003 Next Lecture and Reminders  Next lecture l Dynamic sequential circuits -Reading assignment – Rabaey, et al, 7.3, 7.7  Reminders l Project prototypes due on-line by 5:00pm on Oct 30 th l HW#4 due November 11 th (not Nov 4 th as on outline) l HW#5 will be optional (due November 20 th ) l Final exam scheduled -Tuesday, December 16 th from 10:10 to noon in TBD l Project final reports due December 5 th