1. Chapter 3 - Digital LogicB A
Paul Roper

2. Success is not the key to happiness. Happiness is the key to success.
If you love what you are doing, you will be successful.
BYU CS/ECEn 124
Chapter 3 - Digital Logic
Paul Roper

3. Chapter 3 - Digital Logic
Concepts to Learn…
The Transistor
Devices: Inverter, NAND, NOR, Drivers
De Morgan’s Law
Translations
Decoders, Multiplexors, Adders, PLAs
Logical Completeness
Sequential Logic
Latches
Memory
Finite State Machine
BYU CS/ECEn 124
Chapter 3 - Digital Logic

4. History of the Transistor
Around 1945, Bell Labs scientists discovered that silicon was comprised of two distinct regions differentiated by the way in which they favored current flow.
The area that favored positive current flow they named "p" and the area that favored negative current flow they named "n".
BYU CS/ECEn 124
Chapter 3 - Digital Logic

5. Chapter 3 - Digital Logic
The Transistor
The Transistor Effect
The transistor effect describes the change from a condition of conductivity (switched “on”, full current flow) to a condition of insulation (switched “off”, no current flow).
BYU CS/ECEn 124
Chapter 3 - Digital Logic

6. Digital Logic Circuits
The Transistor
Digital Logic Circuits
Computers = large number of simple structures
Intel 4004 = 2,300 transistors
Intel Pentium 4 = 42 million transistors
Intel Core 2 Duo = 291 million transistors
Intel i7 “Bloomfield” = 731 million transistors
BYU CS/ECEn 124
Chapter 3 - Digital Logic

7. Chapter 3 - Digital Logic
The Transistor
Moore’s Law
2000’s
1990’s
1980’s
1970’s
1960’s
1950’s
1947
Moore’s Law: The number of transistors per area doubles every years.
Early 1900’s
BYU CS/ECEn 124
Chapter 3 - Digital Logic

8. Chapter 3 - Digital Logic
The Transistor
The MOS Transistor
A transistor acts like a switch
conducts current only when "on"
gate
current flow
current flow
gate
Off = open circuit
On = closed circuit
gate FET
0 off
1 on
N-type Transistor
gate FET
0 on
1 off
P-type Transistor
complementary
MOS = metal-oxide semiconductor CMOS = complementary MOS with both N and P transistors
BYU CS/ECEn 124
Chapter 3 - Digital Logic

9. Chapter 3 - Digital Logic
The Transistor
Field Effect Transistor
P type
N type S D G S D G
Gate = Ground = ‘0’
BYU CS/ECEn 124
Chapter 3 - Digital Logic
Paul Roper

10. Chapter 3 - Digital Logic
The Transistor
Field Effect Transistor Operation
P type
N type S D G S D G
Gate = Vcc = ‘1’
BYU CS/ECEn 124
Chapter 3 - Digital Logic
Paul Roper

11. Chapter 3 - Digital Logic
The Transistor
CMOS Gates
We want complementary pull-up and pull-down logic: the pull-down is “on” when the pull-up is “off”, and visa-versa.
Pullup Structure F
Complementary
Pulldown Structure
The “C” in CMOS
Even in the digital world "EVERYTHING IS ANALOG"!
BYU CS/ECEn 124
Chapter 3 - Digital Logic

12. The Inverter in out 0 1 1 0 Digital Logic Devices
out 1 on
off 1 on
off
This is a truth-table. It
tells what the output will be
for all combinations of the
inputs.
Inverter Symbols
in out
0 1
1 0
Symbols are abstractions!
BYU CS/ECEn 124
Chapter 3 - Digital Logic

13. Chapter 3 - Digital Logic
Digital Logic Devices
The NOR Gate (NOT-OR) a b 1
nor on
off 1 1
off on
NOR Symbols
a b nor
BYU CS/ECEn 124
Chapter 3 - Digital Logic

14. Chapter 3 - Digital Logic
Digital Logic Devices
The OR Gate
How do you build an OR gate? a b or a b or
OR Symbol
a b or
BYU CS/ECEn 124
Chapter 3 - Digital Logic

15. The NAND Gate (NOT-AND)
Digital Logic Devices
The NAND Gate (NOT-AND) 1 1 on
off 1 1
off on
NAND b a
NAND Symbols
a b nand
BYU CS/ECEn 124
Chapter 3 - Digital Logic

16. Chapter 3 - Digital Logic
Digital Logic Devices
The AND Gate
How do you build an AND gate?
AND b a
and a b
AND Symbol
a b AND
BYU CS/ECEn 124
Chapter 3 - Digital Logic

17. Chapter 3 - Digital Logic
Digital Logic Devices
Why Inverting Logic? ?
Why can’t we use
N transistors to pull up to Vcc, and
P transistors to pull down to ground?
Because
N transistors do not pass good voltage levels for 1’s
P transistors do not pass good voltage levels for 0’s
It just doesn’t work electronically! So…
Only use P transistors in pull-up structures!
Only use N transistors in pull-down structures!
Pullup Structure
Pulldown Structure F
BYU CS/ECEn 124
Chapter 3 - Digital Logic
Paul Roper

18. Chapter 3 - Digital Logic
Digital Logic Devices
Drivers
Why can’t we use CMOS transistors to connect to a bus?
P transistors to pull up to Vcc, and
N transistors to pull down to ground
Because connecting Vcc to ground let’s the magic smoke out!
Solution: Tri-state driver
BYU CS/ECEn 124
Chapter 3 - Digital Logic

19. De Morgan’s Law To distribute the bar, change the operation.
NOR Symbols
NAND Symbols
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Chapter 3 - Digital Logic

20. Chapter 3 - Digital Logic
De Morgan’s Law
De Morgan’s Proof A B
A + B
A  B 1 1 1 1 1
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Chapter 3 - Digital Logic

21. Reading Functions from Symbols
Translations
Reading Functions from Symbols
The output will be high if
any of the inputs are low...
The output will be low if
all of the inputs are high...
a b out
The output will be high if
the first input is low OR
the second input is high...
It’s just a NAND gate
drawn a different way!!!
BYU CS/ECEn 124
Chapter 3 - Digital Logic

22. You Should Know How to Translate
Translations
You Should Know How to Translate
These are three different ways of representing logical information
Logic Equations
You can convert any one of them to any other
Logic Gates
Truth Tables
BYU CS/ECEn 124
Chapter 3 - Digital Logic

23. From Equations to Gates
Translations
From Equations to Gates
y = NOT(s) AND a AND NOT(b) s a b y y
BYU CS/ECEn 124
Chapter 3 - Digital Logic

24. From Equations to Gates
Translations
From Equations to Gates
y = (~s  a  ~b)
+ (~s  a  b)
+ (s  ~a  b)
+ (s  a  b)
out
BYU CS/ECEn 124
Chapter 3 - Digital Logic

25. From Truth tables to Gates
Translations
From Truth tables to Gates
Each row of truth table is an AND gate
Each output column is an OR gate s
When we write s we mean
the inverse of s or s after it has
gone through an inverter.
s a b out a b s a b
out s a b s a b
BYU CS/ECEn 124
Chapter 3 - Digital Logic

26. From Truth table to Equations
Translations
From Truth table to Equations
Write out truth table a combination of AND’s and OR’s
equivalent to gates
easily converted to gates OR OR OR b a s
out =
s a b out
BYU CS/ECEn 124
Chapter 3 - Digital Logic

27. From Equations to Truth Tables
Translations
From Equations to Truth Tables
For each AND term
fill in the proper row on the truth table OR
Contains a don’t care -
out is independent of b
There is a whole field of
boolean minimization that
capitalizes on this property.
You will learn this in the
next class...
s a b out
s a b out OR OR OR
BYU CS/ECEn 124
Chapter 3 - Digital Logic

28. Manipulating Logic Expressions
Translations
Manipulating Logic Expressions
Laws (basic identities) of Boolean algebra.
Law OR
AND
Identity
x  0 = x
x  1 = x
One/Zero
x  1 = 1
x  0 = 0
Idempotent
x  x = x
x  x = x
Inverse
x  x  = 1
x  x = 0
Commutative
x  y = y  x
x  y = y  x
Associative
(x  y)  z = x  (y  z)
(x  y)  z = x  (y  z)
Distributive
x  (y  z) = (x  y)  (x  z)
x  (y  z) = (x  y)  (x  z)
DeMorgan’s
(x  y) = x  y
(x  y) = x  y
BYU CS/ECEn 124
Chapter 3 - Digital Logic

29. Some Special Function Blocks

30. Chapter 3 - Digital Logic
Circuits
Decoders
Decode the input and signify its value by raising just one of its outputs.
2-to-4
Decoder A B W X Y Z
DECODER Symbol W X Y Z A B
1 if A,B = 00
1 if A,B = 01
1 if A,B = 10
1 if A,B = 11
BYU CS/ECEn 124
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31. Chapter 3 - Digital Logic
Circuits
Decoders
Write the truth table W X Y Z A B
A B W X Y Z
0 0
0 1
1 0
1 1
BYU CS/ECEn 124
Chapter 3 - Digital Logic

32. Circuits
Multiplexors
Connect one of its inputs to its output according to select signals
Useful for selecting one from a collection of data inputs.
Usually has 2n inputs and n select lines.
Symbols are abstractions! A B S C 1
MULTIPLEXOR Symbol A B S C
BYU CS/ECEn 124
Chapter 3 - Digital Logic

33. Chapter 3 - Digital Logic
Circuits
Multiplexors
Write the truth table
A B S C
A simpler way…
A B S C
0 X
1 X X X A B C S 1
BYU CS/ECEn 124
Chapter 3 - Digital Logic

34. Chapter 3 - Digital Logic
Circuits
Adders
At each digit position add together the 2 operands and the carry-in
Full
Adder a0 b0 s0 c0 a1 b1 s1 c1 a2 b2 s2 c2 a3 b3 s3 c3
‘0’ c
0110
+0101
1011
Just like longhand addition
except it’s in binary...
BYU CS/ECEn 124
Chapter 3 - Digital Logic

35. Full Adder Module Design
Circuits
Full Adder Module Design
a b c cyout sum
BYU CS/ECEn 124
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36. Programmable Logic Arrays
PLAs
Programmable Logic Arrays
Programmable Logic Array (PLA) can be used to implement any logic function
Take truth table of any logic function
Convert into equation (any truth table can be expressed as set of “and” expressions “or”ed together)
PLA programmed by making/breaking wire connections ?
Outputs:
Inputs:
BYU CS/ECEn 124
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37. Chapter 3 - Digital Logic
PLAs
PLA Example
Out1 = ABC + ABC + ABC
Out2 = ABC + ABC + ABC
Out3 = ABC + ABC
Inputs
Outputs ? A B C
Out1
Out2
Out3
A B C Out1 Out2 Out3
BYU CS/ECEn 124
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38. Chapter 3 - Digital Logic
Logical Completeness
Logical Completeness
What is the minimum set of gate types needed to implement any logic function?
AND gate, OR gate, INVERTER
DeMorgan’s Theorem
AND gate, INVERTER
OR can be replaced by an AND and three INVERTERS
DeMorgan’s Theorem
OR gate, INVERTER
AND can be replaced by an OR and three INVERTERS
BYU CS/ECEn 124
Chapter 3 - Digital Logic
Paul Roper

39. Chapter 3 - Digital Logic
Logical Completeness
Logical Completeness
NAND (by itself) is logically complete if you can implement an INVERTER, AND, and OR gate using only NAND gates.
NAND
INVERTER
AND OR
BYU CS/ECEn 124
Chapter 3 - Digital Logic

40. Combinational vs. Sequential
Sequential Logic
Combinational vs. Sequential
Two types of “combination” locks 30 15 5 10 20 25
Sequential
Success depends on the sequence of values
(e.g, R-13, L-22, R-3). 4 1 8
Combinational
Success depends only on the values, not the order in which they are set.
BYU CS/ECEn 124
Chapter 3 - Digital Logic

41. Chapter 3 - Digital Logic
Sequential Logic
Storage Elements
Everything so far is called combinational
the output is strictly a function of the current inputs
Real computing systems need storage
for holding previously computed values
for remembering its place (state) in the middle of a multi-step operation
Storage elements remember what was stored in them for later retrieval using feedback
BYU CS/ECEn 124
Chapter 3 - Digital Logic

42. Bi-Stability = Key to Memory
Sequential Logic
Bi-Stability = Key to Memory
This is a stable state –
it will sit like this forever 1 1
This is also a stable state –
it will sit like this forever
When there are 2 stable states - a bi-stable circuit…
BYU CS/ECEn 124
Chapter 3 - Digital Logic

43. RS Latch Signals s and r are active low
Sequential Logic
RS Latch
Signals s and r are active low
they change the circuit when they go low
Output q goes high when s goes low
Output q goes low when r goes low
Output q remains the same otherwise s s s q q q
Cross-coupled NAND gates
Note the feedback
same
same q q q r r r
BYU CS/ECEn 124
Chapter 3 - Digital Logic

44. Chapter 3 - Digital Logic
Sequential Logic
RS Latch – Bi-Stable Circuit s s 1 q 1 q 1 q q 1 r r 1 1
This is also a stable state –
it will sit like this forever
This is a stable state –
it will sit like this forever
BYU CS/ECEn 124
Chapter 3 - Digital Logic

45. Chapter 3 - Digital Logic
Sequential Logic
RS Latch (continued) s q q r 1 1 1 1 1 1 1
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Chapter 3 - Digital Logic

46. RS Latch : Next State Table
Sequential Logic
RS Latch : Next State Table
Defines output as a function of inputs (s and r) and current output (q, its state)
s r q qnext x x q q
not allowed
set
reset
keep old state
BYU CS/ECEn 124
Chapter 3 - Digital Logic

47. Gated D Latch Output q gets value from input d only when we is high
we stands for write enable, think of it as a load signal s r q d we WE
D Q
D-Latch
LATCH Symbol
Symbols are abstractions!
BYU CS/ECEn 124
Chapter 3 - Digital Logic

48. Chapter 3 - Digital Logic
Quiz
1. What is a bi-stable circuit?
2. Draw a logic circuit (using N and P type transistors) for a 3 input NAND gate.
3. With a RS NAND latch, why can’t R and S be low at the same time?
4. How is Q set with the following latch?
BYU CS/ECEn 124
Chapter 3 - Digital Logic

49. Chapter 3 - Digital Logic
Quiz (Answers)
1. What is a bi-stable circuit?
When the circuit has 2 stable states
2. Draw a logic circuit (using N and P type transistors) for a 3 input NAND gate.
BYU CS/ECEn 124
Chapter 3 - Digital Logic

50. Chapter 3 - Digital Logic
Quiz (Answers)
3. With a RS NAND latch, why can’t R and S be low at the same time?
This state would force both outputs to a logic 1, overriding the feedback latching action.
Outputs Q and Q' must have opposite logic levels.
Results in a “race” condition – final state of the latch cannot be determined.
BYU CS/ECEn 124
Chapter 3 - Digital Logic

51. Chapter 3 - Digital Logic
Quiz (Answers)
4. How is Q set with the following latch?
Q is set by changing input S from a logic 0 to a logic 1 1 1
BYU CS/ECEn 124
Chapter 3 - Digital Logic

52. Chapter 3 - Digital Logic
Latch
Register
A computer register is a place to store a collection of bits
Very fast memory
Numbered right to left (LSB on the right) d3 d2 d1 d0 we d
D-Latch
D-Latch
D-Latch
D-Latch we
Register q
REGISTER Symbol q3 q2 q1 q0
BYU CS/ECEn 124
Chapter 3 - Digital Logic

53. Chapter 3 - Digital Logic
Memory
Memory
A collection of addressable locations
Address selects which location to read from or write to
A memory with n address wires has 2n locations.
The number of data wires in equal the number of data wires out.
Memory is changed with we is asserted.
q always reflects the contents stored at the addressed memory location.
Memory can be viewed as a large collection of slower registers.
Memory
address q n we d m
BYU CS/ECEn 124
Chapter 3 - Digital Logic

54. Memory Usage Memory Power-Up State (random bits) BYU CS/ECEn 124
addr value
addr value
addr value
addr value
addr => 101
data => 0000
we => 1
addr => 101
data => 0000
we => 0
addr => 111
data => 1100
we => 1
Power-Up State (random bits)
addr value
addr value
addr value
addr => 000
data => 0000
we => 1
addr => 000
data => 0110
we => 1
addr => 110
data => 0110
we => 0
BYU CS/ECEn 124
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55. Building a Memory From Latches
writeEnable
d input q0
2-to-4
Decoder 00 we
Register q1 01 we
Register
q output q2 10 we
Register q3 11 we
Register a1 a0
MEMORY Symbol
Memory
address q n we d m
This is a functional view.
The key parts are:
address decoder
memory cells (registers)
output selector (mux)
address
n = 2
BYU CS/ECEn 124
Chapter 3 - Digital Logic

56. Chapter 3 - Digital Logic
Memory
Address Space
When we say a computer has a 4GB (giga-byte) address space we mean
it has enough address lines to address 232 address locations
Kilobyte = 210 or bytes
Megabyte = 220 or bytes
Gigabyte = 230 or bytes
Tera-byte = 240 or bytes
Peta-byte = 250 or bytes
BYU CS/ECEn 124
Chapter 3 - Digital Logic

57. Chapter 3 - Digital Logic
Memory
A 12-Bit Memory
4 words, each 3 bits wide
Word line “00”
Word line “01”
Only one word line is high at any given time.
Word line “10”
Word line “11”
Latch
BYU CS/ECEn 124
Chapter 3 - Digital Logic

58. Chapter 3 - Digital Logic
Memory
Reading A 12-Bit Memory
Each column forms a sort of multiplexor
Only one of the AND gates in the column will be enabled. Thus, they allow one row out of 4 to be selected for reading.
BYU CS/ECEn 124
Chapter 3 - Digital Logic

59. Chapter 3 - Digital Logic
Memory
Writing A 12-Bit Memory
4 words, each 3 bits wide
Write line “00”
Write line “01”
Write enable signal and write enable AND gates
Write line “10”
Write line “11”
Depending on state of we signal, zero or one write lines will be high at any given time.
Latch
BYU CS/ECEn 124
Chapter 3 - Digital Logic

60. The MSP430 Finite State Machine
You may not know how it works, but you know the parts its made from!
Program Counter
Status Register
Register
Memory
Multiplexor
Memory
Mapped I/O
Bus Driver
16 16-bit
Registers
Instruction Register
Arithmetic Logic Unit
Lots of Gates
BYU CS/ECEn 124
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61. Chapter 3 - Digital Logic
START HERE
BYU CS/ECEn 124
Chapter 3 - Digital Logic

62. Sequential State Machine
Finite State Machine
Sequential State Machine
Another type of sequential circuit
Combines combinational logic with storage
“Remembers” state, and changes output (and state) based on inputs and current state
State Machine
Inputs
Outputs
Combinational
Logic Circuit
Storage
Elements
BYU CS/ECEn 124
Chapter 3 - Digital Logic

63. Chapter 3 - Digital Logic
Finite State Machine
State of a System
The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken.
Examples:
The state of a basketball game can be represented by the scoreboard (ie. number of points, time remaining, possession, etc.)
The state of a tic-tac-toe game can be represented by the placement of X’s and O’s on the board.
BYU CS/ECEn 124
Chapter 3 - Digital Logic

64. Combinational vs. Sequential
Finite State Machine
Combinational vs. Sequential
Two types of “combination” locks 30 15 5 10 20 25 4 1 8
Combinational
Success depends only on the values, not the order in which they are set.
Sequential
Success depends on the sequence of values
(e.g, R-13, L-22, R-3).
BYU CS/ECEn 124
Chapter 3 - Digital Logic

65. State of Sequential Lock
Finite State Machine
State of Sequential Lock
Our lock example has four different states, labeled A-D:
A: The lock is not open, and no relevant operations have been performed.
B: The lock is not open, and the user has completed the R-13 operation.
C: The lock is not open, and the user has completed R-13, followed by L-22.
D: The lock is open.
BYU CS/ECEn 124
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66. Chapter 3 - Digital Logic
Finite State Machine
State Diagram
Shows states and actions that cause a transition between states.
Open = 0
Open = 0
Open = 0
Open = 1
BYU CS/ECEn 124
Chapter 3 - Digital Logic

67. Chapter 3 - Digital Logic
Finite State Machine
Finite State Machine
A description of a system with the following components:
A finite number of states
A finite number of external inputs
A finite number of external outputs
An explicit specification of all state transitions
An explicit specification of what determines each external output value
Often described by a state diagram.
Inputs trigger state transitions.
Outputs are associated with each state (or with each transition).
BYU CS/ECEn 124
Chapter 3 - Digital Logic

68. Chapter 3 - Digital Logic
Finite State Machine
The Clock
Frequently, a clock circuit triggers transition from one state to the next.
At the beginning of each clock cycle, state machine makes a transition, based on the current state and the external (or internal) inputs.
“1”
“0”
time
One
Cycle
BYU CS/ECEn 124
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69. Chapter 3 - Digital Logic
Finite State Machine
FSM Implementation
Combinational logic
Determine outputs and next state.
Storage elements
Maintains state representation.
State Machine
Inputs
Outputs
Combinational
Logic Circuit
Storage
Elements
Clock
BYU CS/ECEn 124
Chapter 3 - Digital Logic

70. Storage: Master-Slave Flipflop
Finite State Machine
Storage: Master-Slave Flipflop
A pair of gated D-latches isolates next state from current state.
0 is the controllling value on a NAND
Low clock is the hold for the latch
High clock will set or reset depending on input (11 is set and 10 is reset)
Key:
Clock high: A holds in the high phase and B either sets or resets (A ignores input)
Clock low: B holds in the low phase and A either sets or resets
During 1st phase (clock=1), previously-computed state becomes current state and is sent to the logic circuit.
During 2nd phase (clock=0), next state, computed by logic circuit, is stored in Latch A.
BYU CS/ECEn 124
Chapter 3 - Digital Logic
Paul Roper

71. Storage: Master-Slave Flipflop
Finite State Machine
Storage: Master-Slave Flipflop
“1”
“0”
time
SET/RESET
HOLD
0 is the controllling value on a NAND
Low clock is the hold for the latch
High clock will set or reset depending on input (11 is set and 10 is reset)
Key:
Clock high: A holds in the high phase and B either sets or resets (A ignores input)
Clock low: B holds in the low phase and A either sets or resets
BYU CS/ECEn 124
Chapter 3 - Digital Logic
Paul Roper

72. Storage: Master-Slave Flipflop
Finite State Machine
Storage: Master-Slave Flipflop
“1”
“0”
time
HOLD
SET/RESET
0 is the controllling value on a NAND
Low clock is the hold for the latch
High clock will set or reset depending on input (11 is set and 10 is reset)
Key:
Clock high: A holds in the high phase and B either sets or resets (A ignores input)
Clock low: B holds in the low phase and A either sets or resets
BYU CS/ECEn 124
Chapter 3 - Digital Logic
Paul Roper

73. Chapter 3 - Digital Logic
Another view
Input
Combinational Logic
Slave
Master
LOW
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74. Chapter 3 - Digital Logic
Another view
Input
Combinational Logic
Slave
Master
LOW
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75. Chapter 3 - Digital Logic
Another view
Input
Combinational Logic
Slave
Master
HIGH
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76. Chapter 3 - Digital Logic
Another view
Input
Combinational Logic
Slave
Master
HIGH
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77. Chapter 3 - Digital Logic
Another view
Input
Combinational Logic
Slave
Master
HIGH
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78. Chapter 3 - Digital Logic
Another view
Input
Combinational Logic
Slave
Master
LOW
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79. Chapter 3 - Digital Logic
Another view
Input
Combinational Logic
Slave
Master
LOW
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80. Chapter 3 - Digital Logic
Finite State Machine
Storage Elements
Each master-slave flip flop stores one state bit.
The number of storage elements (flip flops) needed is determined by the number of states (and the representation of each state).
Examples:
Sequential lock
4 states – 2 bits
Basketball scoreboard
7 bits for each score, 5 bits for minutes, 6 bits for seconds, 1 bit for possession arrow, 1 bit for half, …
Blinking traffic sign
BYU CS/ECEn 124
Chapter 3 - Digital Logic

81. Finite State Machine Example
A blinking traffic sign
No lights on
1 & 2 on
1, 2, 3, & 4 on
1, 2, 3, 4, & 5 on
Repeat as long as switch is turned on 3 4 1 5 2
DANGER MOVE RIGHT
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82. Traffic Sign State Diagram
Finite State Machine
Traffic Sign State Diagram
Switch on
Switch off
Transition on each clock cycle.
State bit S1
State bit S0
Outputs
BYU CS/ECEn 124
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83. Traffic Sign Truth Tables
Finite State Machine
Traffic Sign Truth Tables
Outputs
(depend only on state: S1S0)
Next State: S1'S0' (depend on state and input)
Switch
Lights 1 and 2
Lights 3 and 4 In S1 S0
S1'
S0' X 1
Light 5 S1 S0 Z Y X 1
Whenever In=0, next state is 00.
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84. Chapter 3 - Digital Logic
Finite State Machine
Traffic Sign Logic
BYU CS/ECEn 124
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85. Chapter 3 - Digital Logic
Finite State Machine
From Logic to Data Path
The data path of a computer is all the logic used to process information.
See the data path of the LC-3 on next slide.
Combinational Logic
Decoders -- convert instructions into control signals
Multiplexers -- select inputs and outputs
ALU (Arithmetic and Logic Unit) -- operations on data
Sequential Logic
State machine -- coordinate control signals and data movement
Registers and latches -- storage elements
BYU CS/ECEn 124
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86. Chapter 3 - Digital Logic
STOP HERE
BYU CS/ECEn 124
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87. MSP430 Finite State Machine
DECODE:NOCLK:MOV||EVSRC
EVDST:CLK1:MOV,Rd|D,ROX=Rd|STORE
EVSRC:CLK1:MOV,Rs|S,ROX=Rs|EVDST
STORE:CLK1:MOV,Rd|ALU,RWE,RIX=Rd|FETCH
...
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88. Chapter 3 - Digital Logic
BYU CS/ECEn 124
Chapter 3 - Digital Logic
Paul Roper

89. Review…

90. Signals, Logic Operators, Gates
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91. Variations in Gate Symbols
Gates with more than two inputs and/or with inverted signals at input or output.
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92. Gates as Control Elements
An AND gate and a tristate buffer act as controlled switches or valves. An inverting buffer is logically the same as a NOT gate.
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93. Wired OR and Bus Connections
Wired OR allows tying together of several controlled signals.
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94. Boolean Functions / Expressions
Ways of specifying a logic function
 Truth table: 2n row, “don’t-care” in input or output
 Logic expression: w  (x  y  z), product-of-sums,
sum-of-products, equivalent expressions
 Word statement: Alarm will sound if the door
is opened while the security system is engaged,
or when the smoke detector is triggered
 Logic circuit diagram: Synthesis vs analysis
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95. Manipulating Logic Expressions
Laws (basic identities) of Boolean algebra.
Name of law
OR version
AND version
Identity
x  0 = x
x 1 = x
One/Zero
x  1 = 1
x 0 = 0
Idempotent
x  x = x
x x = x
Inverse
x  x  = 1
x x  = 0
Commutative
x  y = y  x
x y = y x
Associative
(x  y)  z = x  (y  z)
(x y) z = x (y z)
Distributive
x  (y z) = (x  y) (x  z)
x (y  z) = (x y)  (x z)
DeMorgan’s
(x  y) = x  y 
(x y) = x   y 
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96. Designing Gate Networks
 AND-OR, NAND-NAND, OR-AND, NOR-NOR
 Logic optimization: cost, speed, power dissipation
A two-level AND-OR circuit and two equivalent circuits.
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97. BCD-to-Seven-Segment Decoder
The logic circuit that generates the enable signal for the lowermost segment (number 3) in a seven-segment display unit.
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98. Useful Combinational Parts
 High-level building blocks
 Much like prefab parts used in building a house
 Arithmetic components will be covered in Part III
(adders, multipliers, ALUs)
 Here we cover three useful parts:
multiplexers, decoders/demultiplexers, encoders
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99. Chapter 3 - Digital Logic
Multiplexers
Multiplexer (mux), or selector, allows one of several inputs to be selected and routed to output depending on the binary value of a set of selection or address signals provided to it.
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100. Decoders/Demultiplexers
A decoder allows the selection of one of 2a options using an a-bit address as input. A demultiplexer (demux) is a decoder that only selects an output if its enable signal is asserted.
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101. Chapter 3 - Digital Logic
Encoders
A 2a-to-a encoder outputs an a-bit binary number equal to the index of the single 1 among its 2a inputs.
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102. Programmable Combinational Parts
A programmable combinational part can do the job of many gates or gate networks
Programmed by cutting existing connections (fuses) or establishing new connections (antifuses)
 Programmable ROM (PROM)
 Programmable array logic (PAL)
 Programmable logic array (PLA)
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103. Chapter 3 - Digital Logic
PROMs
Programmable connections and their use in a PROM.
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104. Chapter 3 - Digital Logic
PALs and PLAs
Programmable combinational logic: general structure and two classes known as PAL and PLA devices. Not shown is PROM with fixed AND array (a decoder) and programmable OR array.
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Chapter 3 - Digital Logic

105. Latches, Flip-Flops, and Registers
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106. Chapter 3 - Digital Logic
Latches vs Flip-Flops
Operations of D latch and negative-edge-triggered D flip-flop.
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107. R/W FFs in the Same Cycle
Register-to-register operation with edge-triggered flip-flops.
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108. Finite-State Machines
State table and state diagram for a vending machine coin reception unit.
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109. Chapter 3 - Digital Logic
Register File and FIFO
Register file with random access and FIFO.
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110. Chapter 3 - Digital Logic
SRAM
SRAM memory is simply a large, single-port register file.
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111. Programmable Sequential Parts
A programmable sequential part contain gates and memory elements
Programmed by cutting existing connections (fuses) or establishing new connections (antifuses)
 Programmable array logic (PAL)
 Field-programmable gate array (FPGA)
 Both types contain macrocells and interconnects
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112. From Components to Applications
Subfields or views in computer system engineering.
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113. High- vs Low-Level Programming
More abstract, machine-independent;
easier to write, read, debug, maintain
More concrete, machine-dependent; error
-prone, harder to write, read, debug, maintain
Swap v[i]
and v[i+1]
Very high-
level language
objectives
or tasks
Interpreter
temp=v[i];
v[i]=v[i+1];
v[i+1]=temp;
High-level
language
statements
One task =
Many instructions
Compiler
MOV.B 0x0001(SP),R14
MOV.W SP,R15
INCD.W R15
ADD.W R15,R14
MOV.B @R14,0x0000(SP)
INC.W R14
MOV.B 0x0001(SP),R13
ADD.W R15,R13
MOV.B @R14,0x0000(R13)
MOV.B 0x0001(SP),R15
INC.W R15
MOV.W SP,R14
INCD.W R14
MOV.B @SP,0x0000(R14)
Assembly
language
instruction,
mnemonic
One statement =
Several instructions
Assembler
415E 0001
410F
532F
5F0E
4EE1 0000
531E
415D 0001
5F0D
4EED 0000
415F 0001
531F
410E
532E
41EE 0000
Machine
language
instructions
binary (hex)
Mostly one
for one
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